forked from Elron_dev/elbear_arduino_bsp
ready to alpha
подготовка к альфа-тестированию
This commit is contained in:
khristolyubov committed
commit
e36b851783
164 files changed
+27352
No files matched your search
@@ -0,0 +1,52 @@
|
||||
# Prerequisites
|
||||
*.d
|
||||
|
||||
# Object files
|
||||
*.o
|
||||
*.ko
|
||||
*.obj
|
||||
*.elf
|
||||
|
||||
# Linker output
|
||||
*.ilk
|
||||
*.map
|
||||
*.exp
|
||||
|
||||
# Precompiled Headers
|
||||
*.gch
|
||||
*.pch
|
||||
|
||||
# Libraries
|
||||
*.lib
|
||||
*.a
|
||||
*.la
|
||||
*.lo
|
||||
|
||||
# Shared objects (inc. Windows DLLs)
|
||||
*.dll
|
||||
*.so
|
||||
*.so.*
|
||||
*.dylib
|
||||
|
||||
# Executables
|
||||
*.exe
|
||||
*.out
|
||||
*.app
|
||||
*.i*86
|
||||
*.x86_64
|
||||
*.hex
|
||||
|
||||
# Debug files
|
||||
*.dSYM/
|
||||
*.su
|
||||
*.idb
|
||||
*.pdb
|
||||
|
||||
# Kernel Module Compile Results
|
||||
*.mod*
|
||||
*.cmd
|
||||
.tmp_versions/
|
||||
modules.order
|
||||
Module.symvers
|
||||
Mkfile.old
|
||||
dkms.conf
|
||||
@@ -0,0 +1,13 @@
|
||||
# mik32v2-shared
|
||||
|
||||
The repository contains header files, startup files, linking scripts and some basic libraries related to MIK32 V2
|
||||
|
||||
* include/ - header files of the controller core
|
||||
* mcu32_memory_map.h - memory map, bus clocking masks, interrupt lines and DMA
|
||||
* ldscripts/ - linker scripts
|
||||
* eeprom.ld - loading from ROM
|
||||
* ram.ld - loading from RAM
|
||||
* spifi.ld - loading from SPIFI
|
||||
* libs/ - periphery libraries
|
||||
* periphery/ - periphery register header files
|
||||
* runtime/crt0.S - start file
|
||||
@@ -0,0 +1,119 @@
|
||||
/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
|
||||
/// @file <csr.h>
|
||||
/// Architecture specific CSR's defs and inlines
|
||||
|
||||
#ifndef SCR_CSR_H
|
||||
#define SCR_CSR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define __xstringify(s) __stringify(s)
|
||||
#define __stringify(s) #s
|
||||
|
||||
#ifdef read_csr
|
||||
#undef read_csr
|
||||
#endif
|
||||
|
||||
#ifdef write_csr
|
||||
#undef write_csr
|
||||
#endif
|
||||
|
||||
#ifdef swap_csr
|
||||
#undef swap_csr
|
||||
#endif
|
||||
|
||||
#ifdef set_csr
|
||||
#undef set_csr
|
||||
#endif
|
||||
|
||||
#ifdef clear_csr
|
||||
#undef clear_csr
|
||||
#endif
|
||||
|
||||
#ifdef rdtime
|
||||
#undef rdtime
|
||||
#endif
|
||||
|
||||
#ifdef rdcycle
|
||||
#undef rdcycle
|
||||
#endif
|
||||
|
||||
#ifdef rdinstret
|
||||
#undef rdinstret
|
||||
#endif
|
||||
|
||||
#define read_csr(reg) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
asm volatile ("csrr %0, " __xstringify(reg) : "=r"(__tmp)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define write_csr(reg, val) \
|
||||
do { \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrw " __xstringify(reg) ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrw " __xstringify(reg) ", %0" :: "r"(val)); \
|
||||
} while (0)
|
||||
|
||||
#define swap_csr(reg, val) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(val) && (val) == 0) \
|
||||
asm volatile ("csrrw %0, " __xstringify(reg) ", zero" : "=r"(__tmp) :); \
|
||||
else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(val)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define set_csr(reg, bit) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (bit) < 32) \
|
||||
asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define clear_csr(reg, bit) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (bit) < 32) \
|
||||
asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define rdtime() read_csr(time)
|
||||
#define rdcycle() read_csr(cycle)
|
||||
#define rdinstret() read_csr(instret)
|
||||
|
||||
static inline unsigned long __attribute__((const)) cpuid()
|
||||
{
|
||||
unsigned long res;
|
||||
asm ("csrr %0, mcpuid" : "=r"(res));
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline unsigned long __attribute__((const)) impid()
|
||||
{
|
||||
unsigned long res;
|
||||
asm ("csrr %0, mimpid" : "=r"(res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SCR_CSR_H
|
||||
@@ -0,0 +1,250 @@
|
||||
#ifndef MCU32_MEMORY_MAP_H_INCLUDED
|
||||
#define MCU32_MEMORY_MAP_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EEPROM_BASE_ADDRESS 0x01000000
|
||||
#define EEPROM_SIZE (16*1024)
|
||||
|
||||
#define RAM_BASE_ADDRESS 0x02000000
|
||||
#define RAM_SIZE (16*1024)
|
||||
|
||||
#define SPIFI_BASE_ADDRESS 0x80000000
|
||||
#define SPIFI_SIZE (2*1024*1024)
|
||||
|
||||
#define BOOT_BASE_ADDRESS 0x00000000
|
||||
#define BOOT_SIZE (16*1024)
|
||||
|
||||
#define APB_PERIPH_STEP 0x00000400
|
||||
|
||||
#define DMA_CONFIG_BASE_ADDRESS 0x000040000
|
||||
|
||||
#define APB_DOM_0_BASE_ADDRESS 0x000050000
|
||||
#define PM_BASE_ADDRESS 0x000050000
|
||||
#define EPIC_BASE_ADDRESS 0x000050400
|
||||
#define TIMER32_0_BASE_ADDRESS 0x000050800
|
||||
#define PAD_CONFIG_BASE_ADDRESS 0x000050c00
|
||||
#define WDT_BUS_BASE_ADDRESS 0x000051000
|
||||
#define OTP_BASE_ADDRESS 0x000051400
|
||||
#define PVD_CONTROL_BASE_ADDRESS 0x000051800
|
||||
|
||||
#define WU_BASE_ADDRESS 0x00060000
|
||||
#define RTC_BASE_ADDRESS 0x00060400
|
||||
#define BOOT_MANAGER_BASE_ADDRESS 0x00060800
|
||||
|
||||
#define SPIFI_CONFIG_BASE_ADDRESS 0x00070000
|
||||
#define EEPROM_REGS_BASE_ADDRESS 0x00070400
|
||||
#define CRYPTO_BASE_ADDRESS 0x00080000
|
||||
#define CRC_BASE_ADDRESS 0x00080400
|
||||
|
||||
#define APB_DOM_3_BASE_ADDRESS 0x00081000
|
||||
|
||||
#define WDT_BASE_ADDRESS 0x00081000
|
||||
#define UART_0_BASE_ADDRESS 0x00081400
|
||||
#define UART_1_BASE_ADDRESS 0x00081800
|
||||
#define TIMER16_0_BASE_ADDRESS 0x00081C00
|
||||
#define TIMER16_1_BASE_ADDRESS 0x00082000
|
||||
#define TIMER16_2_BASE_ADDRESS 0x00082400
|
||||
#define TIMER32_1_BASE_ADDRESS 0x00082800
|
||||
#define TIMER32_2_BASE_ADDRESS 0x00082C00
|
||||
#define SPI_0_BASE_ADDRESS 0x00083000
|
||||
#define SPI_1_BASE_ADDRESS 0x00083400
|
||||
#define I2C_0_BASE_ADDRESS 0x00083800
|
||||
#define I2C_1_BASE_ADDRESS 0x00083C00
|
||||
#define GPIO_0_BASE_ADDRESS 0x00084000
|
||||
#define GPIO_1_BASE_ADDRESS 0x00084400
|
||||
#define GPIO_2_BASE_ADDRESS 0x00084800
|
||||
#define GPIO_IRQ_BASE_ADDRESS 0x00084C00
|
||||
#define ANALOG_REG_BASE_ADDRESS 0x00085000
|
||||
|
||||
|
||||
#define SCR1_TIMER_BASE_ADDRESS 0x00490000
|
||||
|
||||
|
||||
#define DMA_CONFIG (( DMA_CONFIG_TypeDef *) DMA_CONFIG_BASE_ADDRESS )
|
||||
|
||||
#define PM (( PM_TypeDef *) PM_BASE_ADDRESS )
|
||||
#define EPIC (( EPIC_TypeDef *) EPIC_BASE_ADDRESS )
|
||||
#define TIMER32_0 (( TIMER32_TypeDef *) TIMER32_0_BASE_ADDRESS )
|
||||
#define PVD_CONTROL (( PVD_CONTROL_TypeDef *) PVD_CONTROL_BASE_ADDRESS )
|
||||
#define PAD_CONFIG (( PAD_CONFIG_TypeDef *) PAD_CONFIG_BASE_ADDRESS )
|
||||
#define WDT_BUS (( WDT_BUS_TypeDef *) WDT_BUS_BASE_ADDRESS )
|
||||
#define OTP (( OTP_TypeDef *) OTP_BASE_ADDRESS )
|
||||
|
||||
#define WU (( WU_TypeDef *) WU_BASE_ADDRESS )
|
||||
#define RTC (( RTC_TypeDef *) RTC_BASE_ADDRESS )
|
||||
#define BOOT_MANAGER (( BOOT_MANAGER_TypeDef *) BOOT_MANAGER_BASE_ADDRESS )
|
||||
|
||||
#define SPIFI_CONFIG (( SPIFI_CONFIG_TypeDef *) SPIFI_CONFIG_BASE_ADDRESS )
|
||||
#define EEPROM_REGS (( EEPROM_REGS_TypeDef *) EEPROM_REGS_BASE_ADDRESS )
|
||||
#define CRYPTO (( CRYPTO_TypeDef *) CRYPTO_BASE_ADDRESS )
|
||||
#define CRC (( CRC_TypeDef *) CRC_BASE_ADDRESS )
|
||||
|
||||
#define WDT (( WDT_TypeDef *) WDT_BASE_ADDRESS )
|
||||
#define UART_0 (( UART_TypeDef *) UART_0_BASE_ADDRESS )
|
||||
#define UART_1 (( UART_TypeDef *) UART_1_BASE_ADDRESS )
|
||||
#define TIMER16_0 (( TIMER16_TypeDef *) TIMER16_0_BASE_ADDRESS )
|
||||
#define TIMER16_1 (( TIMER16_TypeDef *) TIMER16_1_BASE_ADDRESS )
|
||||
#define TIMER16_2 (( TIMER16_TypeDef *) TIMER16_2_BASE_ADDRESS )
|
||||
#define TIMER32_1 (( TIMER32_TypeDef *) TIMER32_1_BASE_ADDRESS )
|
||||
#define TIMER32_2 (( TIMER32_TypeDef *) TIMER32_2_BASE_ADDRESS )
|
||||
#define SPI_0 (( SPI_TypeDef *) SPI_0_BASE_ADDRESS )
|
||||
#define SPI_1 (( SPI_TypeDef *) SPI_1_BASE_ADDRESS )
|
||||
#define I2C_0 (( I2C_TypeDef *) I2C_0_BASE_ADDRESS )
|
||||
#define I2C_1 (( I2C_TypeDef *) I2C_1_BASE_ADDRESS )
|
||||
#define GPIO_0 (( GPIO_TypeDef *) GPIO_0_BASE_ADDRESS )
|
||||
#define GPIO_1 (( GPIO_TypeDef *) GPIO_1_BASE_ADDRESS )
|
||||
#define GPIO_2 (( GPIO_TypeDef *) GPIO_2_BASE_ADDRESS )
|
||||
#define GPIO_IRQ (( GPIO_IRQ_TypeDef *) GPIO_IRQ_BASE_ADDRESS )
|
||||
#define ANALOG_REG (( ANALOG_REG_TypeDef *) ANALOG_REG_BASE_ADDRESS )
|
||||
|
||||
#define SCR1_TIMER (( SCR1_TIMER_TypeDef *) SCR1_TIMER_BASE_ADDRESS )
|
||||
|
||||
|
||||
|
||||
// Clock gating masks to be used with PM module
|
||||
//AHB BUS
|
||||
#define PM_CLOCK_AHB_CPU_S 0
|
||||
#define PM_CLOCK_AHB_CPU_M (1 << PM_CLOCK_AHB_CPU_S)
|
||||
#define PM_CLOCK_AHB_EEPROM_S 1
|
||||
#define PM_CLOCK_AHB_EEPROM_M (1 << PM_CLOCK_AHB_EEPROM_S)
|
||||
#define PM_CLOCK_AHB_RAM_S 2
|
||||
#define PM_CLOCK_AHB_RAM_M (1 << PM_CLOCK_AHB_RAM_S)
|
||||
#define PM_CLOCK_AHB_SPIFI_S 3
|
||||
#define PM_CLOCK_AHB_SPIFI_M (1 << PM_CLOCK_AHB_SPIFI_S)
|
||||
#define PM_CLOCK_AHB_TCB_S 4
|
||||
#define PM_CLOCK_AHB_TCB_M (1 << PM_CLOCK_AHB_TCB_S)
|
||||
#define PM_CLOCK_AHB_DMA_S 5
|
||||
#define PM_CLOCK_AHB_DMA_M (1 << PM_CLOCK_AHB_DMA_S)
|
||||
#define PM_CLOCK_AHB_CRYPTO_S 6
|
||||
#define PM_CLOCK_AHB_CRYPTO_M (1 << PM_CLOCK_AHB_CRYPTO_S)
|
||||
#define PM_CLOCK_AHB_CRC32_S 7
|
||||
#define PM_CLOCK_AHB_CRC32_M (1 << PM_CLOCK_AHB_CRC32_S)
|
||||
|
||||
|
||||
//APB M BUS
|
||||
#define PM_CLOCK_APB_M_PM_S 0
|
||||
#define PM_CLOCK_APB_M_PM_M (1 << PM_CLOCK_APB_M_PM_S)
|
||||
#define PM_CLOCK_APB_M_EPIC_S 1
|
||||
#define PM_CLOCK_APB_M_EPIC_M (1 << PM_CLOCK_APB_M_EPIC_S)
|
||||
#define PM_CLOCK_APB_M_TIMER32_0_S 2
|
||||
#define PM_CLOCK_APB_M_TIMER32_0_M (1 << PM_CLOCK_APB_M_TIMER32_0_S)
|
||||
#define PM_CLOCK_APB_M_PAD_CONFIG_S 3
|
||||
#define PM_CLOCK_APB_M_PAD_CONFIG_M (1 << PM_CLOCK_APB_M_PAD_CONFIG_S)
|
||||
#define PM_CLOCK_APB_M_WDT_BUS_S 4
|
||||
#define PM_CLOCK_APB_M_WDT_BUS_M (1 << PM_CLOCK_APB_M_WDT_BUS_S)
|
||||
#define PM_CLOCK_APB_M_OTP_CONTROLLER_S 5
|
||||
#define PM_CLOCK_APB_M_OTP_CONTROLLER_M (1 << PM_CLOCK_APB_M_OTP_CONTROLLER_S)
|
||||
#define PM_CLOCK_APB_M_PVD_CONTROL_S 6
|
||||
#define PM_CLOCK_APB_M_PVD_CONTROL_M (1 << PM_CLOCK_APB_M_PVD_CONTROL_S)
|
||||
#define PM_CLOCK_APB_M_WU_S 7
|
||||
#define PM_CLOCK_APB_M_WU_M (1 << PM_CLOCK_APB_M_WU_S)
|
||||
#define PM_CLOCK_APB_M_RTC_S 8
|
||||
#define PM_CLOCK_APB_M_RTC_M (1 << PM_CLOCK_APB_M_RTC_S)
|
||||
|
||||
//APB P BUS
|
||||
#define PM_CLOCK_APB_P_WDT_S 0
|
||||
#define PM_CLOCK_APB_P_WDT_M (1 << PM_CLOCK_APB_P_WDT_S)
|
||||
#define PM_CLOCK_APB_P_UART_0_S 1
|
||||
#define PM_CLOCK_APB_P_UART_0_M (1 << PM_CLOCK_APB_P_UART_0_S)
|
||||
#define PM_CLOCK_APB_P_UART_1_S 2
|
||||
#define PM_CLOCK_APB_P_UART_1_M (1 << PM_CLOCK_APB_P_UART_1_S)
|
||||
#define PM_CLOCK_APB_P_TIMER16_0_S 3
|
||||
#define PM_CLOCK_APB_P_TIMER16_0_M (1 << PM_CLOCK_APB_P_TIMER16_0_S)
|
||||
#define PM_CLOCK_APB_P_TIMER16_1_S 4
|
||||
#define PM_CLOCK_APB_P_TIMER16_1_M (1 << PM_CLOCK_APB_P_TIMER16_1_S)
|
||||
#define PM_CLOCK_APB_P_TIMER16_2_S 5
|
||||
#define PM_CLOCK_APB_P_TIMER16_2_M (1 << PM_CLOCK_APB_P_TIMER16_2_S)
|
||||
#define PM_CLOCK_APB_P_TIMER32_1_S 6
|
||||
#define PM_CLOCK_APB_P_TIMER32_1_M (1 << PM_CLOCK_APB_P_TIMER32_1_S)
|
||||
#define PM_CLOCK_APB_P_TIMER32_2_S 7
|
||||
#define PM_CLOCK_APB_P_TIMER32_2_M (1 << PM_CLOCK_APB_P_TIMER32_2_S)
|
||||
#define PM_CLOCK_APB_P_SPI_0_S 8
|
||||
#define PM_CLOCK_APB_P_SPI_0_M (1 << PM_CLOCK_APB_P_SPI_0_S)
|
||||
#define PM_CLOCK_APB_P_SPI_1_S 9
|
||||
#define PM_CLOCK_APB_P_SPI_1_M (1 << PM_CLOCK_APB_P_SPI_1_S)
|
||||
#define PM_CLOCK_APB_P_I2C_0_S 10
|
||||
#define PM_CLOCK_APB_P_I2C_0_M (1 << PM_CLOCK_APB_P_I2C_0_S)
|
||||
#define PM_CLOCK_APB_P_I2C_1_S 11
|
||||
#define PM_CLOCK_APB_P_I2C_1_M (1 << PM_CLOCK_APB_P_I2C_1_S)
|
||||
#define PM_CLOCK_APB_P_GPIO_0_S 12
|
||||
#define PM_CLOCK_APB_P_GPIO_0_M (1 << PM_CLOCK_APB_P_GPIO_0_S)
|
||||
#define PM_CLOCK_APB_P_GPIO_1_S 13
|
||||
#define PM_CLOCK_APB_P_GPIO_1_M (1 << PM_CLOCK_APB_P_GPIO_1_S)
|
||||
#define PM_CLOCK_APB_P_GPIO_2_S 14
|
||||
#define PM_CLOCK_APB_P_GPIO_2_M (1 << PM_CLOCK_APB_P_GPIO_2_S)
|
||||
#define PM_CLOCK_APB_P_ANALOG_REGS_S 15
|
||||
#define PM_CLOCK_APB_P_ANALOG_REGS_M (1 << PM_CLOCK_APB_P_ANALOG_REGS_S)
|
||||
#define PM_CLOCK_APB_P_GPIO_IRQ_S 16
|
||||
#define PM_CLOCK_APB_P_GPIO_IRQ_M (1 << PM_CLOCK_APB_P_GPIO_IRQ_S)
|
||||
|
||||
// Timer connection to PM multiplexor controling timer inputs
|
||||
//
|
||||
#define PM_TIMER32_0_INDEX 0
|
||||
#define PM_TIMER32_1_INDEX 1
|
||||
#define PM_TIMER32_2_INDEX 2
|
||||
#define PM_TIMER16_0_INDEX 3
|
||||
#define PM_TIMER16_1_INDEX 4
|
||||
#define PM_TIMER16_2_INDEX 5
|
||||
|
||||
|
||||
// Interrupt lines to be used with EPIC module
|
||||
//
|
||||
#define EPIC_TIMER32_0_INDEX 0
|
||||
#define EPIC_UART_0_INDEX 1
|
||||
#define EPIC_UART_1_INDEX 2
|
||||
#define EPIC_SPI_0_INDEX 3
|
||||
#define EPIC_SPI_1_INDEX 4
|
||||
#define EPIC_GPIO_IRQ_INDEX 5
|
||||
#define EPIC_I2C_0_INDEX 6
|
||||
#define EPIC_I2C_1_INDEX 7
|
||||
#define EPIC_WDT_INDEX 8
|
||||
#define EPIC_TIMER16_0_INDEX 9
|
||||
#define EPIC_TIMER16_1_INDEX 10
|
||||
#define EPIC_TIMER16_2_INDEX 11
|
||||
#define EPIC_TIMER32_1_INDEX 12
|
||||
#define EPIC_TIMER32_2_INDEX 13
|
||||
#define EPIC_SPIFI_INDEX 14
|
||||
#define EPIC_RTC_INDEX 15
|
||||
#define EPIC_EEPROM_INDEX 16
|
||||
#define EPIC_WDT_DOM3_INDEX 17
|
||||
#define EPIC_WDT_SPIFI_INDEX 18
|
||||
#define EPIC_WDT_EEPROM_INDEX 19
|
||||
#define EPIC_DMA_INDEX 20
|
||||
#define EPIC_FREQ_MON_INDEX 21
|
||||
#define EPIC_PVD_AVCC_UNDER 22
|
||||
#define EPIC_PVD_AVCC_OVER 23
|
||||
#define EPIC_PVD_VCC_UNDER 24
|
||||
#define EPIC_PVD_VCC_OVER 25
|
||||
#define EPIC_BATTERY_NON_GOOD 26
|
||||
#define EPIC_BOR_INDEX 27
|
||||
#define EPIC_TSENS_INDEX 28
|
||||
#define EPIC_ADC_INDEX 29
|
||||
#define EPIC_DAC0_INDEX 30
|
||||
#define EPIC_DAC1_INDEX 31
|
||||
|
||||
|
||||
// DMA request lines
|
||||
//
|
||||
#define DMA_UART_0_INDEX 0
|
||||
#define DMA_UART_1_INDEX 1
|
||||
#define DMA_CRYPTO_INDEX 2
|
||||
#define DMA_SPI_0_INDEX 3
|
||||
#define DMA_SPI_1_INDEX 4
|
||||
#define DMA_I2C_0_INDEX 5
|
||||
#define DMA_I2C_1_INDEX 6
|
||||
#define DMA_SPIFI_INDEX 7
|
||||
#define DMA_TIMER32_1_INDEX 8
|
||||
#define DMA_TIMER32_2_INDEX 9
|
||||
#define DMA_DAC0_INDEX 10
|
||||
#define DMA_DAC1_INDEX 11
|
||||
#define DMA_TIMER32_0_INDEX 12
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // MCU32_MEMORY_MAP_H_INCLUDED
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,88 @@
|
||||
|
||||
#ifndef SCR1_CSR_ENCODING_H
|
||||
#define SCR1_CSR_ENCODING_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Bit mask and register value list is based on
|
||||
// SCR1 External Architecture Specification
|
||||
// (3.2.4. Machine Mode Standard CSRs)
|
||||
|
||||
#define MVENDORID_VALUE 0x0
|
||||
#define MARCHID_VALUE 0x8
|
||||
#define MIMPID_VALUE 0x19083000
|
||||
|
||||
// MSTATUS masks
|
||||
//
|
||||
#define MSTATUS_MIE (0x1 << 3)
|
||||
#define MSTATUS_MPIE (0x1 << 7)
|
||||
#define MSTATUS_MPP (0x3 << 11)
|
||||
|
||||
// MISA
|
||||
//
|
||||
#define MISA_RVC (0x1 << 2)
|
||||
#define MISA_RVE (0x1 << 4)
|
||||
#define MISA_RVI (0x1 << 8)
|
||||
#define MISA_RVM (0x1 << 12)
|
||||
#define MISA_RVX (0x1 << 23)
|
||||
#define MISA_MXL (0x3 << 30)
|
||||
|
||||
// MIE
|
||||
//
|
||||
#define MIE_MSIE (0x1 << 3)
|
||||
#define MIE_MTIE (0x1 << 7)
|
||||
#define MIE_MEIE (0x1 << 11)
|
||||
|
||||
// MTVEC
|
||||
//
|
||||
#define MTVEC_MODE (0x3 << 0)
|
||||
#define MTVEC_MODE_DIRECT (0x0 << 0)
|
||||
#define MTVEC_MODE_VECTORED (0x1 << 0)
|
||||
#define MTVEC_BASE (0xFFFFFFFF & 0xFFFFFFC0)
|
||||
|
||||
// MSCRATCH
|
||||
// MEPC
|
||||
|
||||
// MCAUSE
|
||||
//
|
||||
#define MCAUSE_EC (0xF << 0)
|
||||
#define MCAUSE_INT (0x1 << 31)
|
||||
#define MCAUSE_INSTRUCTION_ADDRESS_MISALIGNED 0
|
||||
#define MCAUSE_INSTRUCTION_ACCESS_FAULT 1
|
||||
#define MCAUSE_ILLEGAL_INSTRUCTION 2
|
||||
#define MCAUSE_BREAKPOINT 3
|
||||
#define MCAUSE_LOAD_ADDRESS_MISSALIGNED 4
|
||||
#define MCAUSE_LOAD_ACCESS_FAULT 5
|
||||
#define MCAUSE_STORE_ADDRESS_MISALIGNED 6
|
||||
#define MCAUSE_STORE_ACCESS_FAULT 7
|
||||
//
|
||||
#define MCAUSE_ECALL_FROM_M_MODE 11
|
||||
//
|
||||
#define MCAUSE_MACHINE_SOFTWARE_INTERRUPT 0x80000003
|
||||
#define MCAUSE_MACHINE_TIMER_INTERRUPT 0x80000007
|
||||
#define MCAUSE_MACHINE_EXTERNAL_INTERRUPT 0x8000000B
|
||||
|
||||
// MTVAL
|
||||
|
||||
// MIP
|
||||
//
|
||||
#define MIP_MSIP (0x1 << 3)
|
||||
#define MIP_MTIP (0x1 << 7)
|
||||
#define MIP_MEIP (0x1 << 11)
|
||||
|
||||
// MCYCLE
|
||||
// MCYCLEH
|
||||
// MINSTRET
|
||||
// MINSTRETH
|
||||
|
||||
// MCOUNTEN
|
||||
#define MCOUNTEN_CY (1 << 0)
|
||||
#define MCOUNTEN_IR (1 << 2)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,35 @@
|
||||
#ifndef __SCR1__SPECIFIC
|
||||
#define __SCR1__SPECIFIC
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define mcounten 0x7E0
|
||||
|
||||
// Memory-mapped registers
|
||||
#define mtime_base 0x00490000
|
||||
#define mtime_ctrl_offs 0x00
|
||||
#define mtime_div_offs 0x04
|
||||
#define mtime_offs 0x08
|
||||
#define mtimeh_offs 0x0C
|
||||
#define mtimecmp_offs 0x10
|
||||
#define mtimecmph_offs 0x14
|
||||
#define mtime_ctrl mtime_base+mtime_ctrl_offs
|
||||
#define mtime_div mtime_base+mtime_div_offs
|
||||
#define mtime mtime_base+mtime_offs
|
||||
#define mtimeh mtime_base+mtimeh_offs
|
||||
#define mtimecmp mtime_base+mtimecmp_offs
|
||||
#define mtimecmph mtime_base+mtimecmph_offs
|
||||
|
||||
#define SCR1_MTIME_CTRL_EN 0
|
||||
#define SCR1_MTIME_CTRL_CLKSRC 1
|
||||
|
||||
#define SCR1_MTIME_CTRL_WR_MASK 0x3
|
||||
#define SCR1_MTIME_DIV_WR_MASK 0x3FF
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _SCR1__SPECIFIC
|
||||
@@ -0,0 +1,92 @@
|
||||
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
|
||||
MEMORY {
|
||||
rom (RX): ORIGIN = 0x01000000, LENGTH = 8K
|
||||
ram (RWX): ORIGIN = 0x02000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
STACK_SIZE = 1024;
|
||||
|
||||
CL_SIZE = 16;
|
||||
|
||||
SECTIONS {
|
||||
.text ORIGIN(rom) : {
|
||||
PROVIDE(__TEXT_START__ = .);
|
||||
*crt0.o(.text .text.*)
|
||||
*(.text.smallsysteminit)
|
||||
*(.text.SmallSystemInit)
|
||||
. = ORIGIN(rom) + 0xC0;
|
||||
KEEP(*crt0.o(.trap_text))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__TEXT_END__ = .);
|
||||
} >rom
|
||||
|
||||
.data :
|
||||
AT( __TEXT_END__ ) {
|
||||
PROVIDE(__DATA_START__ = .);
|
||||
_gp = .;
|
||||
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
*(.data .data.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
__DATA_IMAGE_START__ = LOADADDR(.data);
|
||||
__DATA_IMAGE_END__ = LOADADDR(.data) + SIZEOF(.data);
|
||||
ASSERT(__DATA_IMAGE_END__ < ORIGIN(rom) + LENGTH(rom), "Data image overflows rom section")
|
||||
|
||||
/* thread-local data segment */
|
||||
.tdata : {
|
||||
PROVIDE(_tls_data = .);
|
||||
PROVIDE(_tdata_begin = .);
|
||||
*(.tdata .tdata.*)
|
||||
PROVIDE(_tdata_end = .);
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
.tbss : {
|
||||
PROVIDE(__BSS_START__ = .);
|
||||
*(.tbss .tbss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(_tbss_end = .);
|
||||
} >ram
|
||||
|
||||
/* bss segment */
|
||||
.sbss : {
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >ram
|
||||
|
||||
.bss : {
|
||||
*(.bss .bss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__BSS_END__ = .);
|
||||
} >ram
|
||||
|
||||
_end = .;
|
||||
PROVIDE(__end = .);
|
||||
|
||||
/* End of uninitalized data segement */
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - STACK_SIZE : {
|
||||
FILL(0);
|
||||
PROVIDE(__STACK_START__ = .);
|
||||
. += STACK_SIZE;
|
||||
PROVIDE(__C_STACK_TOP__ = .);
|
||||
PROVIDE(__STACK_END__ = .);
|
||||
} >ram
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.eh_frame .eh_frame.*)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,98 @@
|
||||
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
|
||||
MEMORY {
|
||||
boot : ORIGIN = 0x00000000, LENGTH = 16K
|
||||
ram : ORIGIN = 0x02000000, LENGTH = 16K
|
||||
spifi : ORIGIN = 0x80000000, LENGTH = DEFINED(SPIFI_LENGTH) ? SPIFI_LENGTH : 256M
|
||||
}
|
||||
|
||||
STACK_SIZE = 1024;
|
||||
|
||||
CL_SIZE = 16;
|
||||
|
||||
SECTIONS {
|
||||
.boot :
|
||||
AT(ORIGIN(spifi)) {
|
||||
PROVIDE(__BOOT_START__ = .);
|
||||
*crt0.o(.text .text.*)
|
||||
*(.boot)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__BOOT_END__ = .);
|
||||
} > boot
|
||||
|
||||
|
||||
/* Placeholder for boot section */
|
||||
.text ORIGIN(spifi) + SIZEOF(.boot) : {
|
||||
|
||||
PROVIDE(__TEXT_START__ = .);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__TEXT_END__ = .);
|
||||
} > spifi
|
||||
|
||||
.data :
|
||||
AT( ALIGN(__TEXT_END__, CL_SIZE) ) {
|
||||
PROVIDE(__DATA_START__ = .);
|
||||
_gp = .;
|
||||
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
*(.data .data.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
} > ram
|
||||
|
||||
__DATA_IMAGE_START__ = LOADADDR(.data);
|
||||
__DATA_IMAGE_END__ = LOADADDR(.data) + SIZEOF(.data);
|
||||
ASSERT(__DATA_IMAGE_END__ < ORIGIN(spifi) + LENGTH(spifi), "Data image overflows spifi section")
|
||||
|
||||
/* bss segment */
|
||||
.sbss : {
|
||||
PROVIDE(__BSS_START__ = .);
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} > ram
|
||||
|
||||
.bss : {
|
||||
*(.bss .bss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__BSS_END__ = .);
|
||||
} > ram
|
||||
|
||||
|
||||
/* Code intended to be copied to RAM before execution */
|
||||
.ram_text :
|
||||
AT( ALIGN(__DATA_IMAGE_END__, CL_SIZE) ) {
|
||||
PROVIDE(__RAM_TEXT_START__ = .);
|
||||
*(.ram_text)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__RAM_TEXT_END__ = .);
|
||||
} > ram
|
||||
|
||||
__RAM_TEXT_IMAGE_START__ = LOADADDR(.ram_text);
|
||||
__RAM_TEXT_IMAGE_END__ = LOADADDR(.ram_text) + SIZEOF(.ram_text);
|
||||
ASSERT(__RAM_TEXT_IMAGE_END__ < ORIGIN(spifi) + LENGTH(spifi), "RAM text image overflows spifi section")
|
||||
|
||||
_end = .;
|
||||
PROVIDE(__end = .);
|
||||
|
||||
/* End of uninitalized data segement */
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - STACK_SIZE : {
|
||||
FILL(0);
|
||||
PROVIDE(__STACK_START__ = .);
|
||||
. += STACK_SIZE;
|
||||
PROVIDE(__C_STACK_TOP__ = .);
|
||||
PROVIDE(__STACK_END__ = .);
|
||||
} > ram
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.eh_frame .eh_frame.*)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,91 @@
|
||||
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
|
||||
MEMORY {
|
||||
ram (RWX): ORIGIN = 0x02000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
STACK_SIZE = 1024;
|
||||
|
||||
CL_SIZE = 16;
|
||||
|
||||
SECTIONS {
|
||||
.text ORIGIN(ram) : {
|
||||
PROVIDE(__TEXT_START__ = .);
|
||||
*crt0.o(.text .text.*)
|
||||
*(.text.smallsysteminit)
|
||||
*(.text.SmallSystemInit)
|
||||
. = ORIGIN(ram) + 0xC0;
|
||||
KEEP(*crt0.o(.trap_text))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__TEXT_END__ = .);
|
||||
} >ram
|
||||
|
||||
.data :
|
||||
AT( __TEXT_END__ ) {
|
||||
PROVIDE(__DATA_START__ = .);
|
||||
_gp = .;
|
||||
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
*(.data .data.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
__DATA_IMAGE_START__ = LOADADDR(.data);
|
||||
__DATA_IMAGE_END__ = LOADADDR(.data) + SIZEOF(.data);
|
||||
ASSERT(__DATA_IMAGE_END__ < ORIGIN(ram) + LENGTH(ram) - STACK_SIZE, "Data image overflows ram section")
|
||||
|
||||
/* thread-local data segment */
|
||||
.tdata : {
|
||||
PROVIDE(_tls_data = .);
|
||||
PROVIDE(_tdata_begin = .);
|
||||
*(.tdata .tdata.*)
|
||||
PROVIDE(_tdata_end = .);
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
.tbss : {
|
||||
PROVIDE(__BSS_START__ = .);
|
||||
*(.tbss .tbss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(_tbss_end = .);
|
||||
} >ram
|
||||
|
||||
/* bss segment */
|
||||
.sbss : {
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >ram
|
||||
|
||||
.bss : {
|
||||
*(.bss .bss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__BSS_END__ = .);
|
||||
} >ram
|
||||
|
||||
_end = .;
|
||||
PROVIDE(__end = .);
|
||||
|
||||
/* End of uninitalized data segement */
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - STACK_SIZE : {
|
||||
FILL(0);
|
||||
PROVIDE(__STACK_START__ = .);
|
||||
. += STACK_SIZE;
|
||||
PROVIDE(__C_STACK_TOP__ = .);
|
||||
PROVIDE(__STACK_END__ = .);
|
||||
} >ram
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.eh_frame .eh_frame.*)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,92 @@
|
||||
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
|
||||
MEMORY {
|
||||
rom (RX): ORIGIN = 0x02000000, LENGTH = 8K
|
||||
ram (RWX): ORIGIN = 0x02002000, LENGTH = 8K
|
||||
}
|
||||
|
||||
STACK_SIZE = 1024;
|
||||
|
||||
CL_SIZE = 16;
|
||||
|
||||
SECTIONS {
|
||||
.text ORIGIN(rom) : {
|
||||
PROVIDE(__TEXT_START__ = .);
|
||||
*crt0.o(.text .text.*)
|
||||
*(.text.smallsysteminit)
|
||||
*(.text.SmallSystemInit)
|
||||
. = ORIGIN(rom) + 0xC0;
|
||||
KEEP(*crt0.o(.trap_text))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__TEXT_END__ = .);
|
||||
} >rom
|
||||
|
||||
.data :
|
||||
AT( __TEXT_END__ ) {
|
||||
PROVIDE(__DATA_START__ = .);
|
||||
_gp = .;
|
||||
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
*(.data .data.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
__DATA_IMAGE_START__ = LOADADDR(.data);
|
||||
__DATA_IMAGE_END__ = LOADADDR(.data) + SIZEOF(.data);
|
||||
ASSERT(__DATA_IMAGE_END__ < ORIGIN(rom) + LENGTH(rom), "Data image overflows rom section")
|
||||
|
||||
/* thread-local data segment */
|
||||
.tdata : {
|
||||
PROVIDE(_tls_data = .);
|
||||
PROVIDE(_tdata_begin = .);
|
||||
*(.tdata .tdata.*)
|
||||
PROVIDE(_tdata_end = .);
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
.tbss : {
|
||||
PROVIDE(__BSS_START__ = .);
|
||||
*(.tbss .tbss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(_tbss_end = .);
|
||||
} >ram
|
||||
|
||||
/* bss segment */
|
||||
.sbss : {
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >ram
|
||||
|
||||
.bss : {
|
||||
*(.bss .bss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__BSS_END__ = .);
|
||||
} >ram
|
||||
|
||||
_end = .;
|
||||
PROVIDE(__end = .);
|
||||
|
||||
/* End of uninitalized data segement */
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - STACK_SIZE : {
|
||||
FILL(0);
|
||||
PROVIDE(__STACK_START__ = .);
|
||||
. += STACK_SIZE;
|
||||
PROVIDE(__C_STACK_TOP__ = .);
|
||||
PROVIDE(__STACK_END__ = .);
|
||||
} >ram
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.eh_frame .eh_frame.*)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,92 @@
|
||||
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
|
||||
MEMORY {
|
||||
rom (RX): ORIGIN = 0x80000000, LENGTH = 256M
|
||||
ram (RWX): ORIGIN = 0x02000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
STACK_SIZE = 1024;
|
||||
|
||||
CL_SIZE = 16;
|
||||
|
||||
SECTIONS {
|
||||
.text ORIGIN(rom) : {
|
||||
PROVIDE(__TEXT_START__ = .);
|
||||
*crt0.S.o(.text .text.*)
|
||||
*(.text.smallsysteminit)
|
||||
*(.text.SmallSystemInit)
|
||||
. = 0xC0;
|
||||
KEEP(*crt0.S.o(.trap_text))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__TEXT_END__ = .);
|
||||
} >rom
|
||||
|
||||
.data :
|
||||
AT( __TEXT_END__ ) {
|
||||
PROVIDE(__DATA_START__ = .);
|
||||
_gp = .;
|
||||
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
*(.data .data.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
__DATA_IMAGE_START__ = LOADADDR(.data);
|
||||
__DATA_IMAGE_END__ = LOADADDR(.data) + SIZEOF(.data);
|
||||
ASSERT(__DATA_IMAGE_END__ < ORIGIN(rom) + LENGTH(rom), "Data image overflows rom section")
|
||||
|
||||
/* thread-local data segment */
|
||||
.tdata : {
|
||||
PROVIDE(_tls_data = .);
|
||||
PROVIDE(_tdata_begin = .);
|
||||
*(.tdata .tdata.*)
|
||||
PROVIDE(_tdata_end = .);
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
.tbss : {
|
||||
PROVIDE(__BSS_START__ = .);
|
||||
*(.tbss .tbss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(_tbss_end = .);
|
||||
} >ram
|
||||
|
||||
/* bss segment */
|
||||
.sbss : {
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >ram
|
||||
|
||||
.bss : {
|
||||
*(.bss .bss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__BSS_END__ = .);
|
||||
} >ram
|
||||
|
||||
_end = .;
|
||||
PROVIDE(__end = .);
|
||||
|
||||
/* End of uninitalized data segement */
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - STACK_SIZE : {
|
||||
FILL(0);
|
||||
PROVIDE(__STACK_START__ = .);
|
||||
. += STACK_SIZE;
|
||||
PROVIDE(__C_STACK_TOP__ = .);
|
||||
PROVIDE(__STACK_END__ = .);
|
||||
} >ram
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.eh_frame .eh_frame.*)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,114 @@
|
||||
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
|
||||
MEMORY {
|
||||
rom (RX): ORIGIN = 0x80000000, LENGTH = 256M
|
||||
ram (RWX): ORIGIN = 0x02000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
STACK_SIZE = 1024;
|
||||
HEAP_SIZE = 1024;
|
||||
|
||||
CL_SIZE = 16;
|
||||
|
||||
SECTIONS {
|
||||
.text ORIGIN(rom) : {
|
||||
PROVIDE(__TEXT_START__ = .);
|
||||
*crt0.S.o(.text .text.*)
|
||||
*(.text.smallsysteminit)
|
||||
*(.text.SmallSystemInit)
|
||||
. = ORIGIN(rom) + 0xC0;
|
||||
KEEP(*crt0.S.o(.trap_text))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >rom
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
PROVIDE(__TEXT_END__ = .);
|
||||
} >rom AT>rom
|
||||
|
||||
.data :
|
||||
AT( __TEXT_END__ ) {
|
||||
PROVIDE(__DATA_START__ = .);
|
||||
_gp = .;
|
||||
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
|
||||
*(.sdata .sdata.* .sdata* .sdata*.* .gnu.linkonce.s.*)
|
||||
*(.data .data.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
__DATA_IMAGE_START__ = LOADADDR(.data);
|
||||
__DATA_IMAGE_END__ = LOADADDR(.data) + SIZEOF(.data);
|
||||
ASSERT(__DATA_IMAGE_END__ < ORIGIN(rom) + LENGTH(rom), "Data image overflows rom section")
|
||||
|
||||
/* thread-local data segment */
|
||||
.tdata : {
|
||||
PROVIDE(_tls_data = .);
|
||||
PROVIDE(_tdata_begin = .);
|
||||
*(.tdata .tdata.*)
|
||||
PROVIDE(_tdata_end = .);
|
||||
. = ALIGN(CL_SIZE);
|
||||
} >ram
|
||||
|
||||
.tbss : {
|
||||
PROVIDE(__BSS_START__ = .);
|
||||
*(.tbss .tbss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(_tbss_end = .);
|
||||
} >ram
|
||||
|
||||
/* bss segment */
|
||||
.sbss : {
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >ram
|
||||
|
||||
.bss : {
|
||||
*(.bss .bss.*)
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__BSS_END__ = .);
|
||||
} >ram
|
||||
|
||||
.heap : {
|
||||
PROVIDE(__heap_start = .);
|
||||
. += HEAP_SIZE;
|
||||
. = ALIGN(CL_SIZE);
|
||||
PROVIDE(__heap_end = .);
|
||||
} >ram
|
||||
|
||||
_end = .;
|
||||
PROVIDE(__end = .);
|
||||
|
||||
/* End of uninitalized data segement */
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - STACK_SIZE : {
|
||||
FILL(0);
|
||||
PROVIDE(__STACK_START__ = .);
|
||||
. += STACK_SIZE;
|
||||
PROVIDE(__C_STACK_TOP__ = .);
|
||||
PROVIDE(__STACK_END__ = .);
|
||||
} >ram
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.eh_frame .eh_frame.*)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,133 @@
|
||||
|
||||
|
||||
#include "dma_lib.h"
|
||||
|
||||
|
||||
|
||||
|
||||
void DMA_StartNewTask(DMA_CONFIG_TypeDef* dma, uint32_t channel_index,
|
||||
uint32_t control_value,
|
||||
uint32_t source_address, uint32_t destination_address, uint32_t length)
|
||||
{
|
||||
|
||||
|
||||
dma->CHANNELS[channel_index].SRC = source_address;
|
||||
dma->CHANNELS[channel_index].DST = destination_address;
|
||||
dma->CHANNELS[channel_index].LEN = length;
|
||||
dma->CHANNELS[channel_index].CFG = control_value | DMA_CH_CFG_ENABLE_M;
|
||||
}
|
||||
|
||||
void DMA_Wait (DMA_CONFIG_TypeDef* dma, uint32_t channel_index)
|
||||
{
|
||||
|
||||
// uint32_t channel_bits = 0;
|
||||
|
||||
while ((dma->CONFIG_STATUS & ((1 << channel_index) << DMA_STATUS_READY_S)) == 0) ;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
void DMA_StartNewLlTask(DMA_CONFIG_TypeDef* dma, uint32_t channel_index,
|
||||
uint32_t task_address)
|
||||
{
|
||||
dma->ENABLE_CH &= ~(1 << channel_index);
|
||||
dma->CHANNELS[channel_index].DMA_Cntrl = DMA_CONTROL_linkListEnable_M;
|
||||
dma->CHANNELS[channel_index].SRC_DESCRIPTOR = task_address;
|
||||
dma->ENABLE_CH |= (1 << channel_index);
|
||||
}
|
||||
|
||||
|
||||
//�������� ��������� �������� � ���������
|
||||
unsigned int DMA_Wait_Timeout (DMA_CONFIG_TypeDef* dma, uint32_t channel_index) {
|
||||
unsigned int TIMEOUT = 30000;
|
||||
unsigned int wait = 0;
|
||||
if ((dma->ENABLE_CH & (1 << channel_index)) == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t channel_bits = 0;
|
||||
channel_bits |= (1 << channel_index) << DMA_DONE_S;
|
||||
channel_bits |= (1 << channel_index) << DMA_PERROR_SRC_S;
|
||||
channel_bits |= (1 << channel_index) << DMA_PERROR_DST_S;
|
||||
|
||||
//�������� ��������� �������� � ���������
|
||||
for(wait=0;wait<TIMEOUT;wait++) {
|
||||
if((dma->DMA_STATUS & channel_bits) != 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(wait==TIMEOUT) {
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//�������� ���������� ������� � ������
|
||||
unsigned int DMA_ChnDone (DMA_CONFIG_TypeDef* dma, uint32_t channel_index) {
|
||||
if ((dma->ENABLE_CH & (1 << channel_index)) == 0) {
|
||||
return DMA_CHN_DONE_ERROR_ENABLE;
|
||||
}
|
||||
|
||||
uint32_t channel_bits = 0;
|
||||
|
||||
//�������� ����������
|
||||
channel_bits = (1 << channel_index) << DMA_DONE_S;
|
||||
if((dma->DMA_STATUS & channel_bits) != 0) {
|
||||
return DMA_CHN_DONE_ERROR_NO;
|
||||
}
|
||||
|
||||
//������ ���������
|
||||
channel_bits = (1 << channel_index) << DMA_PERROR_SRC_S;
|
||||
if((dma->DMA_STATUS & channel_bits) != 0) {
|
||||
return DMA_CHN_DONE_ERROR_SRC;
|
||||
}
|
||||
|
||||
//������ ���������
|
||||
channel_bits = (1 << channel_index) << DMA_PERROR_DST_S;
|
||||
if((dma->DMA_STATUS & channel_bits) != 0) {
|
||||
return DMA_CHN_DONE_ERROR_DST;
|
||||
}
|
||||
|
||||
return DMA_CHN_DONE_NOT_DONE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//�������� ���������� ������� �� ���� �������
|
||||
unsigned int DMA_AllChnDone (DMA_CONFIG_TypeDef* dma) {
|
||||
if (dma->ENABLE_CH != DMA_ENABLE_M) {
|
||||
return DMA_CHN_DONE_ERROR_ENABLE;
|
||||
}
|
||||
|
||||
//�������� ����������
|
||||
if((dma->DMA_STATUS & DMA_DONE_M) == DMA_DONE_M) {
|
||||
return DMA_CHN_DONE_ERROR_NO;
|
||||
}
|
||||
|
||||
//������ ���������
|
||||
if((dma->DMA_STATUS & DMA_PERROR_SRC_M) != 0) {
|
||||
return DMA_CHN_DONE_ERROR_SRC;
|
||||
}
|
||||
|
||||
//������ ���������
|
||||
if((dma->DMA_STATUS & DMA_PERROR_DST_M) != 0) {
|
||||
return DMA_CHN_DONE_ERROR_DST;
|
||||
}
|
||||
|
||||
return DMA_CHN_DONE_NOT_DONE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
#ifndef DMA_LIB_H_INCLUDED
|
||||
#define DMA_LIB_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
#define DMA_CHN_DONE_ERROR_NO 0
|
||||
#define DMA_CHN_DONE_ERROR_SRC 1
|
||||
#define DMA_CHN_DONE_ERROR_DST 2
|
||||
#define DMA_CHN_DONE_ERROR_ENABLE 3
|
||||
#define DMA_CHN_DONE_NOT_DONE 4
|
||||
*/
|
||||
#include "dma_config.h"
|
||||
|
||||
/*
|
||||
Следует пользоваться структурами задач для DMA так, чтобы они не выходили
|
||||
из области видимости и память под ними не использовалась для других целей,
|
||||
пока DMA точно не закончил работать с ними.
|
||||
Например, это относится к созданию переменных этого типа в стеке.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SrcAddress;
|
||||
uint32_t DestAddress;
|
||||
uint32_t LengthBytes;
|
||||
uint32_t Control;
|
||||
} DMA_Task_t;
|
||||
|
||||
|
||||
void DMA_StartNewTask(DMA_CONFIG_TypeDef* dma, uint32_t channel_index,
|
||||
uint32_t control_value,
|
||||
uint32_t source_address, uint32_t destination_address, uint32_t length);
|
||||
|
||||
|
||||
|
||||
|
||||
void DMA_Wait(DMA_CONFIG_TypeDef* dma, uint32_t channel_index);
|
||||
|
||||
/*
|
||||
void DMA_StartNewLlTask(DMA_CONFIG_TypeDef* dma, uint32_t channel_index, uint32_t task_address);
|
||||
|
||||
unsigned int DMA_Wait_Timeout (DMA_CONFIG_TypeDef* dma, uint32_t channel_index);
|
||||
unsigned int DMA_ChnDone (DMA_CONFIG_TypeDef* dma, uint32_t channel_index);
|
||||
unsigned int DMA_AllChnDone (DMA_CONFIG_TypeDef* dma);
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,132 @@
|
||||
|
||||
#include "rtc_lib.h"
|
||||
|
||||
void RTC_Enable(RTC_TypeDef* rtc)
|
||||
{
|
||||
rtc->CTRL |= RTC_CTRL_EN_M;
|
||||
}
|
||||
|
||||
void RTC_Disable(RTC_TypeDef* rtc)
|
||||
{
|
||||
rtc->CTRL &= ~RTC_CTRL_EN_M;
|
||||
}
|
||||
|
||||
void RTC_ClearAlarmFlag(RTC_TypeDef* rtc)
|
||||
{
|
||||
rtc->CTRL &= ~RTC_CTRL_ALRM_M;
|
||||
}
|
||||
|
||||
|
||||
void RTC_WaitDataLoading(RTC_TypeDef* rtc)
|
||||
{
|
||||
while(rtc->CTRL & RTC_CTRL_FLAG_M) ;
|
||||
}
|
||||
|
||||
void RTC_WaitAlarm(RTC_TypeDef* rtc)
|
||||
{
|
||||
while((rtc->CTRL & RTC_CTRL_ALRM_M) == 0) ;
|
||||
}
|
||||
|
||||
|
||||
void RTC_WriteTimeToReg(RTC_TypeDef* rtc, volatile uint32_t* reg,
|
||||
uint8_t hours, uint8_t minutes, uint8_t seconds,
|
||||
uint16_t miliseconds, uint8_t day_of_week
|
||||
)
|
||||
{
|
||||
*reg =
|
||||
((day_of_week << RTC_TIME_DOW_S) & RTC_TIME_DOW_M) |
|
||||
(((hours / 10) << RTC_TIME_TH_S) & RTC_TIME_TH_M) |
|
||||
(((hours % 10) << RTC_TIME_H_S) & RTC_TIME_H_M) |
|
||||
(((minutes / 10) << RTC_TIME_TM_S) & RTC_TIME_TM_M) |
|
||||
(((minutes % 10) << RTC_TIME_M_S) & RTC_TIME_M_M) |
|
||||
(((seconds / 10) << RTC_TIME_TS_S) & RTC_TIME_TS_M) |
|
||||
(((seconds % 10) << RTC_TIME_S_S) & RTC_TIME_S_M) |
|
||||
(((miliseconds / 100) << RTC_TIME_TOS_S) & RTC_TIME_TOS_M);
|
||||
}
|
||||
|
||||
|
||||
void RTC_LoadTime(RTC_TypeDef* rtc,
|
||||
uint8_t hours, uint8_t minutes, uint8_t seconds,
|
||||
uint16_t miliseconds, uint8_t day_of_week
|
||||
)
|
||||
{
|
||||
RTC_WriteTimeToReg(rtc, &(rtc->TIME),
|
||||
hours, minutes, seconds, miliseconds, day_of_week);
|
||||
RTC_WaitDataLoading(rtc);
|
||||
}
|
||||
|
||||
|
||||
void RTC_LoadTimeAlarm(RTC_TypeDef* rtc,
|
||||
uint8_t hours, uint8_t minutes, uint8_t seconds,
|
||||
uint16_t miliseconds, uint8_t day_of_week
|
||||
)
|
||||
{
|
||||
RTC_WriteTimeToReg(rtc, &(rtc->TALRM),
|
||||
hours, minutes, seconds, miliseconds, day_of_week);
|
||||
RTC_WaitDataLoading(rtc);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void RTC_WriteDateToReg(RTC_TypeDef* rtc, volatile uint32_t* reg,
|
||||
uint8_t date, uint8_t month, uint16_t year
|
||||
)
|
||||
{
|
||||
*reg =
|
||||
(((date / 10) << RTC_DATE_TD_S) & RTC_DATE_TD_M) |
|
||||
(((date % 10) << RTC_DATE_D_S) & RTC_DATE_D_M) |
|
||||
(((month / 10) << RTC_DATE_TM_S) & RTC_DATE_TM_M) |
|
||||
(((month % 10) << RTC_DATE_M_S) & RTC_DATE_M_M) |
|
||||
(((year % 10) << RTC_DATE_Y_S) & RTC_DATE_Y_M) |
|
||||
(((year / 10 % 10) << RTC_DATE_TY_S) & RTC_DATE_TY_M) |
|
||||
(((year /100 % 10) << RTC_DATE_C_S) & RTC_DATE_C_M) |
|
||||
(((year / 1000) << RTC_DATE_TC_S) & RTC_DATE_TC_M);
|
||||
}
|
||||
|
||||
void RTC_LoadDate(RTC_TypeDef* rtc,
|
||||
uint8_t date, uint8_t month, uint16_t year
|
||||
)
|
||||
{
|
||||
RTC_WriteDateToReg(rtc, &(rtc->DATE),
|
||||
date, month, year);
|
||||
RTC_WaitDataLoading(rtc);
|
||||
}
|
||||
|
||||
|
||||
void RTC_LoadDateAlarm(RTC_TypeDef* rtc,
|
||||
uint8_t date, uint8_t month, uint16_t year
|
||||
)
|
||||
{
|
||||
RTC_WriteDateToReg(rtc, &(rtc->DALRM),
|
||||
date, month, year);
|
||||
RTC_WaitDataLoading(rtc);
|
||||
}
|
||||
|
||||
|
||||
void RTC_SetAlarmMask(RTC_TypeDef* rtc,
|
||||
bool date, bool month, bool year,
|
||||
bool hours, bool minutes, bool seconds,
|
||||
bool miliseconds, bool day_of_week
|
||||
)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
temp = rtc->TALRM;
|
||||
temp &= ~(RTC_TALRM_CDOW_M | RTC_TALRM_CH_M |
|
||||
RTC_TALRM_CM_M | RTC_TALRM_CS_M | RTC_TALRM_CTOS_M);
|
||||
temp |= (hours ? RTC_TALRM_CH_M : 0) |
|
||||
(minutes ? RTC_TALRM_CM_M : 0) |
|
||||
(seconds ? RTC_TALRM_CS_M : 0) |
|
||||
(miliseconds ? RTC_TALRM_CTOS_M : 0) |
|
||||
(day_of_week ? RTC_TALRM_CDOW_M : 0);
|
||||
rtc->TALRM = temp;
|
||||
|
||||
temp = rtc->DALRM;
|
||||
temp &= ~(RTC_DALRM_CC_M | RTC_DALRM_CY_M |
|
||||
RTC_DALRM_CM_M | RTC_DALRM_CD_M);
|
||||
temp |= (date ? RTC_DALRM_CD_M : 0) |
|
||||
(month ? RTC_DALRM_CM_M : 0) |
|
||||
(year ? (RTC_DALRM_CC_M | RTC_DALRM_CY_M) : 0);
|
||||
rtc->DALRM = temp;
|
||||
|
||||
}
|
||||
@@ -0,0 +1,170 @@
|
||||
#ifndef RTC_LIB_H_INCLUDED
|
||||
#define RTC_LIB_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \file
|
||||
Библиотека для работы с контроллером часов реального времени RTC.
|
||||
*/
|
||||
|
||||
#include "inttypes.h"
|
||||
#include "stdbool.h"
|
||||
|
||||
#include "rtc.h"
|
||||
|
||||
|
||||
/** Запускает RTC
|
||||
|
||||
\note Дата и время должны быть заданы предварительно.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
*/
|
||||
void RTC_Enable(RTC_TypeDef* rtc);
|
||||
|
||||
/** Останавливает RTC
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
*/
|
||||
void RTC_Disable(RTC_TypeDef* rtc);
|
||||
|
||||
/** Сбрасывает флаг будильника
|
||||
|
||||
\note Если текущее время все еще подходит
|
||||
для срабатвания будильника, то флаг выставится вновь.
|
||||
Чтобы этого избежать, можно, например,
|
||||
обнулить маску будильника.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
*/
|
||||
void RTC_ClearAlarmFlag(RTC_TypeDef* rtc);
|
||||
|
||||
|
||||
/** Ожидает завершение синхронизации после записи в регистры RTC
|
||||
|
||||
Функция опрашивает поле FLAG регистра RRTC_CTRL,
|
||||
пока он не станет равным 0.
|
||||
|
||||
\note Когда флаг равен 1,
|
||||
то идет синхронизация данных между доменами
|
||||
и нельзя производить запись в другие регистры RTC.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
*/
|
||||
void RTC_WaitDataLoading(RTC_TypeDef* rtc);
|
||||
|
||||
|
||||
/** Ожидает срабатывания будильника
|
||||
|
||||
Функция опрашивает флаг ALRM регистра RRTC_CTRL,
|
||||
пока он не станет равным 1.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
*/
|
||||
void RTC_WaitAlarm(RTC_TypeDef* rtc);
|
||||
|
||||
|
||||
/** Загружает время и день недели
|
||||
|
||||
\warning Загружаемые значения должны быть корректными.
|
||||
Функция не производит их проверку.
|
||||
|
||||
\note RTC работает с сотнями милисекунд.
|
||||
Значения не кратные 100 будут округляются вниз.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
|
||||
\param hours часы
|
||||
\param minutes минуты
|
||||
\param seconds секунды
|
||||
\param miliseconds милисекунды
|
||||
\param day_of_week порядковый номер дня недели
|
||||
*/
|
||||
void RTC_LoadTime(RTC_TypeDef* rtc,
|
||||
uint8_t hours, uint8_t minutes, uint8_t seconds,
|
||||
uint16_t miliseconds, uint8_t day_of_week
|
||||
);
|
||||
|
||||
/** Загружает время и день недели для будильника
|
||||
|
||||
\warning Загружаемые значения должны быть корректными.
|
||||
Функция не производит их проверку.
|
||||
|
||||
\note RTC работает с сотнями милисекунд.
|
||||
Значения не кратные 100 округляются вниз.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
|
||||
\param hours часы
|
||||
\param minutes минуты
|
||||
\param seconds секунды
|
||||
\param miliseconds милисекунды
|
||||
\param day_of_week порядковый номер дня недели
|
||||
*/
|
||||
void RTC_LoadTimeAlarm(RTC_TypeDef* rtc,
|
||||
uint8_t hours, uint8_t minutes, uint8_t seconds,
|
||||
uint16_t miliseconds, uint8_t day_of_week
|
||||
);
|
||||
|
||||
|
||||
/** Загружает дату
|
||||
|
||||
\warning Загружаемые значения должны быть корректными.
|
||||
Функция не производит их проверку.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
|
||||
\param date число
|
||||
\param month месяц
|
||||
\param year год
|
||||
*/
|
||||
void RTC_LoadDate(RTC_TypeDef* rtc,
|
||||
uint8_t date, uint8_t month, uint16_t year
|
||||
);
|
||||
|
||||
|
||||
/** Загружает дату будильника
|
||||
|
||||
\warning Загружаемые значения должны быть корректными.
|
||||
Функция не производит их проверку.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
|
||||
\param date число
|
||||
\param month месяц
|
||||
\param year год
|
||||
*/
|
||||
void RTC_LoadDateAlarm(RTC_TypeDef* rtc,
|
||||
uint8_t date, uint8_t month, uint16_t year
|
||||
);
|
||||
|
||||
|
||||
/** Устанавливает маску будильника
|
||||
|
||||
Если значение маски равно true,
|
||||
то поле участвует в сравнении при
|
||||
определении срабатывания будильника.
|
||||
|
||||
\param rtc Указатель для доступа к RTC
|
||||
|
||||
\param date число
|
||||
\param month месяц
|
||||
\param year год
|
||||
\param hours часы
|
||||
\param minutes минуты
|
||||
\param seconds секунды
|
||||
\param miliseconds милисекунды
|
||||
\param day_of_week порядковый номер дня недели
|
||||
*/
|
||||
void RTC_SetAlarmMask(RTC_TypeDef* rtc,
|
||||
bool date, bool month, bool year,
|
||||
bool hours, bool minutes, bool seconds,
|
||||
bool miliseconds, bool day_of_week
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // RTC_LIB_H_INCLUDED
|
||||
@@ -0,0 +1,105 @@
|
||||
|
||||
#include "spi_lib.h"
|
||||
|
||||
|
||||
void SPI_CS_Enable(SPI_TypeDef* SPI, unsigned int CS_M) {
|
||||
SPI->CONFIG = (SPI->CONFIG & ~SPI_CONFIG_CS_M) | CS_M;
|
||||
}
|
||||
|
||||
|
||||
void SPI_CS_Disable(SPI_TypeDef* SPI, unsigned int CS_M) {
|
||||
SPI->CONFIG = (SPI->CONFIG & ~SPI_CONFIG_CS_M) | SPI_CONFIG_CS_NONE_M;
|
||||
}
|
||||
|
||||
|
||||
void SPI_Init(SPI_TypeDef* s, uint32_t config)
|
||||
{
|
||||
s->ENABLE = 0;
|
||||
SPI_ClearRxBuffer(s);
|
||||
s->CONFIG = config;
|
||||
s->ENABLE = SPI_ENABLE_M;
|
||||
}
|
||||
|
||||
|
||||
void SPI_WaitTxNotFull(SPI_TypeDef* s)
|
||||
{
|
||||
while ((s->INT_STATUS & SPI_INT_STATUS_TX_FIFO_NOT_FULL_M) == 0) ;
|
||||
}
|
||||
|
||||
int SPI_TimeoutWaitTxNotFull(SPI_TypeDef* s, uint32_t timeout)
|
||||
{
|
||||
while ((s->INT_STATUS & SPI_INT_STATUS_TX_FIFO_NOT_FULL_M) == 0)
|
||||
{
|
||||
if (timeout-- == 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void SPI_WaitRxNotEmpty(SPI_TypeDef* s)
|
||||
{
|
||||
while ((s->INT_STATUS & SPI_INT_STATUS_RX_FIFO_NOT_EMPTY_M) == 0) ;
|
||||
}
|
||||
|
||||
|
||||
int SPI_TimeoutWaitRxNotEmpty(SPI_TypeDef* s, uint32_t timeout)
|
||||
{
|
||||
while ((s->INT_STATUS & SPI_INT_STATUS_RX_FIFO_NOT_EMPTY_M) == 0)
|
||||
{
|
||||
if (timeout-- == 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void SPI_ClearRxBuffer(SPI_TypeDef* s)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
while ((s->INT_STATUS & SPI_INT_STATUS_RX_FIFO_NOT_EMPTY_M) != 0)
|
||||
{
|
||||
dummy = s->RXDATA;
|
||||
}
|
||||
(void) dummy;
|
||||
}
|
||||
|
||||
|
||||
void SPI_Exchange(SPI_TypeDef* s, uint8_t* input_bytes, uint8_t* output_bytes, uint32_t count)
|
||||
{
|
||||
while (count-- > 0)
|
||||
{
|
||||
SPI_WaitTxNotFull(s);
|
||||
s->TXDATA = *input_bytes++;
|
||||
SPI_WaitRxNotEmpty(s);
|
||||
if (output_bytes != 0)
|
||||
{
|
||||
*output_bytes++ = s->RXDATA;
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)s->RXDATA;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
#ifndef SPI_LIB_H_INCLUDED
|
||||
#define SPI_LIB_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "spi_.h"
|
||||
|
||||
|
||||
void SPI_CS_Enable(SPI_TypeDef* SPI, unsigned int CS_M);
|
||||
void SPI_CS_Disable(SPI_TypeDef* SPI, unsigned int CS_M);
|
||||
|
||||
void SPI_Init(SPI_TypeDef* s, uint32_t config);
|
||||
void SPI_WaitTxNotFull(SPI_TypeDef* s);
|
||||
int SPI_TimeoutWaitTxNotFull(SPI_TypeDef* s, uint32_t timeout);
|
||||
void SPI_WaitRxNotEmpty(SPI_TypeDef* s);
|
||||
int SPI_TimeoutWaitRxNotEmpty(SPI_TypeDef* s, uint32_t timeout);
|
||||
void SPI_ClearRxBuffer(SPI_TypeDef* s);
|
||||
|
||||
void SPI_Exchange(SPI_TypeDef* s, uint8_t* input_bytes, uint8_t* output_bytes, uint32_t count);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,149 @@
|
||||
|
||||
#include "uart_lib.h"
|
||||
|
||||
__attribute__((weak)) void HAL_UART_MspInit(UART_TypeDef* uart)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
if (uart == UART_0)
|
||||
{
|
||||
__HAL_PCC_UART_0_CLK_ENABLE();
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_5 | GPIO_PIN_6;
|
||||
GPIO_InitStruct.Mode = HAL_GPIO_MODE_SERIAL;
|
||||
GPIO_InitStruct.Pull = HAL_GPIO_PULL_NONE;
|
||||
HAL_GPIO_Init(GPIO_0, &GPIO_InitStruct);
|
||||
}
|
||||
|
||||
if (uart == UART_1)
|
||||
{
|
||||
__HAL_PCC_UART_1_CLK_ENABLE();
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
|
||||
GPIO_InitStruct.Mode = HAL_GPIO_MODE_SERIAL;
|
||||
GPIO_InitStruct.Pull = HAL_GPIO_PULL_NONE;
|
||||
HAL_GPIO_Init(GPIO_1, &GPIO_InitStruct);
|
||||
}
|
||||
}
|
||||
|
||||
bool UART_Init(UART_TypeDef* uart,
|
||||
uint32_t divider, uint32_t control1,
|
||||
uint32_t control2, uint32_t control3)
|
||||
{
|
||||
HAL_UART_MspInit(uart);
|
||||
|
||||
bool ready;
|
||||
uint32_t flags;
|
||||
|
||||
if (divider < 16)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
uart->CONTROL1 = 0;
|
||||
uart->DIVIDER = divider;
|
||||
uart->FLAGS = 0xFFFFFFFF;
|
||||
|
||||
uart->CONTROL2 = control2;
|
||||
uart->CONTROL3 = control3;
|
||||
uart->CONTROL1 = control1 | UART_CONTROL1_UE_M;
|
||||
|
||||
do
|
||||
{
|
||||
flags = uart->FLAGS;
|
||||
ready = true;
|
||||
if(control1 & UART_CONTROL1_RE_M)
|
||||
{
|
||||
ready = ready && ((flags & UART_FLAGS_REACK_M) != 0);
|
||||
}
|
||||
if(control1 & UART_CONTROL1_TE_M)
|
||||
{
|
||||
ready = ready && ((flags & UART_FLAGS_TEACK_M) != 0);
|
||||
}
|
||||
}
|
||||
while (!ready);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
bool UART_IsTransmissionFinished(UART_TypeDef* uart)
|
||||
{
|
||||
// if ((uart->FLAGS & UART_FLAGS_TC_M) == 0) // с этим флагом есть какая-то доп задержка в стоп-битах длиной почти с бит
|
||||
if ((uart->FLAGS & UART_FLAGS_TXE_M) == 0) // а этот не дожидается по факту окончания передачи, зато со стоп-битами все четко
|
||||
{
|
||||
return false;
|
||||
}
|
||||
else
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
void UART_WaitTransmission(UART_TypeDef* uart)
|
||||
{
|
||||
while (!UART_IsTransmissionFinished(uart)) ;
|
||||
}
|
||||
|
||||
bool UART_IsTxBufferFreed(UART_TypeDef* uart)
|
||||
{
|
||||
return ((uart->FLAGS & UART_FLAGS_TXE_M) != 0);
|
||||
}
|
||||
|
||||
void UART_WriteByte(UART_TypeDef* uart, uint16_t byte)
|
||||
{
|
||||
uart->TXDATA = byte;
|
||||
}
|
||||
|
||||
void UART_Write(UART_TypeDef* uart, uint16_t* byte_array, uint32_t count)
|
||||
{
|
||||
while (count-- > 0)
|
||||
{
|
||||
UART_WriteByte(uart, *byte_array++);
|
||||
UART_WaitTransmission(uart);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool UART_IsRxFifoEmpty(UART_TypeDef* uart)
|
||||
{
|
||||
return ((uart->FLAGS & UART_FLAGS_RXNE_M) == 0);
|
||||
}
|
||||
|
||||
bool UART_IsRxFifoFull(UART_TypeDef* uart)
|
||||
{
|
||||
return (!UART_IsRxFifoEmpty(uart));
|
||||
}
|
||||
|
||||
void UART_WaitReceiving(UART_TypeDef* uart)
|
||||
{
|
||||
while (UART_IsRxFifoEmpty(uart)) ;
|
||||
}
|
||||
|
||||
uint16_t UART_ReadByte(UART_TypeDef* uart)
|
||||
{
|
||||
return (uint16_t)uart->RXDATA;
|
||||
}
|
||||
|
||||
void UART_Read(UART_TypeDef* uart, uint8_t* byte_array, uint32_t count)
|
||||
{
|
||||
while (count-- > 0)
|
||||
{
|
||||
UART_WaitReceiving(uart);
|
||||
*byte_array++ = UART_ReadByte(uart);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void UART_ClearRxFifo(UART_TypeDef* uart)
|
||||
{
|
||||
while (!UART_IsRxFifoEmpty(uart))
|
||||
{
|
||||
(void)uart->RXDATA;
|
||||
}
|
||||
}
|
||||
|
||||
void __attribute__((weak)) xputc(char c)
|
||||
{
|
||||
UART_WriteByte(UART_0, c);
|
||||
UART_WaitTransmission(UART_0);
|
||||
}
|
||||
@@ -0,0 +1,135 @@
|
||||
#ifndef UART_LIB_H_INCLUDED
|
||||
#define UART_LIB_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \file
|
||||
Библиотека для работы с контроллером USART.
|
||||
*/
|
||||
#include "mik32_hal_pcc.h"
|
||||
#include "mik32_hal_gpio.h"
|
||||
#include "inttypes.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "uart.h"
|
||||
#include "mcu32_memory_map.h"
|
||||
|
||||
void HAL_UART_MspInit(UART_TypeDef* uart);
|
||||
|
||||
/** Инициализирует контроллер USART
|
||||
|
||||
Функция задает режим работы и делитель скорости обмена.
|
||||
`Скорость обмена = частоты тактирования контроллера / divider`
|
||||
\warning Делитель должен быть не менее 16
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
\param divider делитель частоты тактирования контроллера
|
||||
\param control1 значение регистра управления 1
|
||||
\param control2 значение регистра управления 2
|
||||
\param control3 значение регистра управления 3
|
||||
|
||||
\return Если инициализация выполнена успешно,
|
||||
то возвращается true
|
||||
|
||||
*/
|
||||
bool UART_Init(UART_TypeDef* uart, uint32_t divider,
|
||||
uint32_t control1, uint32_t control2, uint32_t control3
|
||||
);
|
||||
|
||||
|
||||
/** Определяет, активен ли передатчик модуля
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
|
||||
\return Если передача завершена, возвращается true
|
||||
*/
|
||||
bool UART_IsTransmissionFinished(UART_TypeDef* uart);
|
||||
|
||||
|
||||
/** Ожидает, пока модуль передаст все записанные в буфер байты
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
*/
|
||||
void UART_WaitTransmission(UART_TypeDef* uart);
|
||||
|
||||
|
||||
/** Ожидает, пока модуль примет данные
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
*/
|
||||
void UART_WaitReceiving(UART_TypeDef* uart);
|
||||
|
||||
/** Определяет, был ли байт забран передатчиком из передающего буфера
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
|
||||
\return Если передающий буфер полон, то возвращается true
|
||||
*/
|
||||
bool UART_IsTxBufferFreed(UART_TypeDef* uart);
|
||||
|
||||
/** Определяет, полон ли принимающий буфер
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
|
||||
\return Если в принимающем буфере есть данные, то возвращается true
|
||||
*/
|
||||
bool UART_IsRxFifoFull(UART_TypeDef* uart);
|
||||
|
||||
/** Определяет, пуст ли принимающий буфер
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
|
||||
\return Если в принимающем буфере нет данных, то возвращается true
|
||||
*/
|
||||
bool UART_IsRxFifoEmpty(UART_TypeDef* uart);
|
||||
|
||||
/** Записывает байт в передающий буфер USART
|
||||
Функция записывает байт в передающий буфер.
|
||||
Если перед записью буфер полон,
|
||||
то функция ожидает, пока в буфере не появится место.
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
\param byte отправляемые данные
|
||||
*/
|
||||
void UART_WriteByte(UART_TypeDef* uart, uint16_t byte);
|
||||
|
||||
/** Читает байт из принимающего буфер USART
|
||||
Функция читает байт из принимающего буфера.
|
||||
Если перед чтением буфер пуст,
|
||||
то функция ожидает приема нового байта.
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
|
||||
\return принятые данные
|
||||
*/
|
||||
uint16_t UART_ReadByte(UART_TypeDef* uart);
|
||||
|
||||
/** Записывает массив байт в передающий буфер USART
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
\param byte_array
|
||||
\param count
|
||||
*/
|
||||
void UART_Write(UART_TypeDef* uart, uint16_t* byte_array, uint32_t count);
|
||||
|
||||
/** Читает массив байт из принимающего буфер USART
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
*/
|
||||
void UART_Read(UART_TypeDef* uart, uint8_t* byte_array, uint32_t count);
|
||||
|
||||
/** Очищает принимающий буфер
|
||||
|
||||
\param uart указатель для доступа к UART
|
||||
*/
|
||||
void UART_ClearRxFifo(UART_TypeDef* uart);
|
||||
|
||||
void __attribute__((weak)) xputc(char c);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // UART_LIB_H_INCLUDED
|
||||
@@ -0,0 +1,447 @@
|
||||
/*------------------------------------------------------------------------/
|
||||
/ Universal String Handler for Console Input and Output
|
||||
/-------------------------------------------------------------------------/
|
||||
/
|
||||
/ Copyright (C) 2014, ChaN, all right reserved.
|
||||
/
|
||||
/ xprintf module is an open source software. Redistribution and use of
|
||||
/ xprintf module in source and binary forms, with or without modification,
|
||||
/ are permitted provided that the following condition is met:
|
||||
/
|
||||
/ 1. Redistributions of source code must retain the above copyright notice,
|
||||
/ this condition and the following disclaimer.
|
||||
/
|
||||
/ This software is provided by the copyright holder and contributors "AS IS"
|
||||
/ and any warranties related to this software are DISCLAIMED.
|
||||
/ The copyright owner or contributors be NOT LIABLE for any damages caused
|
||||
/ by use of this software.
|
||||
/
|
||||
/-------------------------------------------------------------------------*/
|
||||
|
||||
#include "xprintf.h"
|
||||
|
||||
|
||||
#if _USE_XFUNC_OUT
|
||||
#include <stdarg.h>
|
||||
void (*xfunc_out)(unsigned char); /* Pointer to the output stream */
|
||||
static char *outptr;
|
||||
|
||||
/*----------------------------------------------*/
|
||||
/* Put a character */
|
||||
/*----------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
void xfputc ( /* Put a character to the specified device */
|
||||
void(*func)(unsigned char), /* Pointer to the output function */
|
||||
char chr /* Character to be put */
|
||||
)
|
||||
{
|
||||
void (*pf)(unsigned char);
|
||||
|
||||
|
||||
pf = xfunc_out; /* Save current output device */
|
||||
xfunc_out = func; /* Switch output to specified device */
|
||||
xputc(chr);
|
||||
xfunc_out = pf; /* Restore output device */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------*/
|
||||
/* Put a null-terminated string */
|
||||
/*----------------------------------------------*/
|
||||
|
||||
void xputs ( /* Put a string to the default device */
|
||||
const char* str /* Pointer to the string */
|
||||
)
|
||||
{
|
||||
while (*str) {
|
||||
xputc(*str++);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void xfputs ( /* Put a string to the specified device */
|
||||
void(*func)(unsigned char), /* Pointer to the output function */
|
||||
const char* str /* Pointer to the string */
|
||||
)
|
||||
{
|
||||
void (*pf)(unsigned char);
|
||||
|
||||
|
||||
pf = xfunc_out; /* Save current output device */
|
||||
xfunc_out = func; /* Switch output to specified device */
|
||||
while (*str) { /* Put the string */
|
||||
xputc(*str++);
|
||||
}
|
||||
xfunc_out = pf; /* Restore output device */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------*/
|
||||
/* Formatted string output */
|
||||
/*----------------------------------------------*/
|
||||
/* xprintf("%d", 1234); "1234"
|
||||
xprintf("%6d,%3d%%", -200, 5); " -200, 5%"
|
||||
xprintf("%-6u", 100); "100 "
|
||||
xprintf("%ld", 12345678); "12345678"
|
||||
xprintf("%llu", 0x100000000); "4294967296" <_USE_LONGLONG>
|
||||
xprintf("%04x", 0xA3); "00a3"
|
||||
xprintf("%08lX", 0x123ABC); "00123ABC"
|
||||
xprintf("%016b", 0x550F); "0101010100001111"
|
||||
xprintf("%*d", 6, 100); " 100"
|
||||
xprintf("%s", "String"); "String"
|
||||
xprintf("%-5s", "abc"); "abc "
|
||||
xprintf("%5s", "abc"); " abc"
|
||||
xprintf("%c", 'a'); "a"
|
||||
xprintf("%f", 10.0); <xprintf lacks floating point support. Use regular printf.>
|
||||
*/
|
||||
|
||||
static
|
||||
void xvprintf (
|
||||
const char* fmt, /* Pointer to the format string */
|
||||
va_list arp /* Pointer to arguments */
|
||||
)
|
||||
{
|
||||
unsigned int r, i, j, w, f;
|
||||
int n;
|
||||
char s[32], c, d, *p;
|
||||
#if _USE_LONGLONG
|
||||
_LONGLONG_t v;
|
||||
unsigned _LONGLONG_t vs;
|
||||
#else
|
||||
long v;
|
||||
unsigned long vs;
|
||||
#endif
|
||||
|
||||
|
||||
for (;;) {
|
||||
c = *fmt++; /* Get a format character */
|
||||
if (!c) break; /* End of format? */
|
||||
if (c != '%') { /* Pass it through if not a % sequense */
|
||||
xputc(c); continue;
|
||||
}
|
||||
f = w = 0; /* Clear parms */
|
||||
c = *fmt++; /* Get first char of the sequense */
|
||||
if (c == '0') { /* Flag: left '0' padded */
|
||||
f = 1; c = *fmt++;
|
||||
} else {
|
||||
if (c == '-') { /* Flag: left justified */
|
||||
f = 2; c = *fmt++;
|
||||
}
|
||||
}
|
||||
if (c == '*') { /* Minimum width from an argument */
|
||||
n = va_arg(arp, int);
|
||||
if (n < 0) { /* Flag: left justified */
|
||||
n = 0 - n;
|
||||
f = 2;
|
||||
}
|
||||
w = n; c = *fmt++;
|
||||
} else {
|
||||
while (c >= '0' && c <= '9') { /* Minimum width */
|
||||
w = w * 10 + c - '0';
|
||||
c = *fmt++;
|
||||
}
|
||||
}
|
||||
if (c == 'l' || c == 'L') { /* Prefix: Size is long */
|
||||
f |= 4; c = *fmt++;
|
||||
#if _USE_LONGLONG
|
||||
if (c == 'l' || c == 'L') { /* Prefix: Size is long long */
|
||||
f |= 8; c = *fmt++;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
if (!c) break; /* End of format? */
|
||||
d = c;
|
||||
if (d >= 'a') d -= 0x20;
|
||||
switch (d) { /* Type is... */
|
||||
case 'S' : /* String */
|
||||
p = va_arg(arp, char*);
|
||||
for (j = 0; p[j]; j++) ;
|
||||
while (!(f & 2) && j++ < w) xputc(' ');
|
||||
xputs(p);
|
||||
while (j++ < w) xputc(' ');
|
||||
continue;
|
||||
case 'C' : /* Character */
|
||||
xputc((char)va_arg(arp, int)); continue;
|
||||
case 'B' : /* Binary */
|
||||
r = 2; break;
|
||||
case 'O' : /* Octal */
|
||||
r = 8; break;
|
||||
case 'D' : /* Signed decimal */
|
||||
case 'U' : /* Unsigned decimal */
|
||||
r = 10; break;
|
||||
case 'X' : /* Hexdecimal */
|
||||
r = 16; break;
|
||||
default: /* Unknown type (passthrough) */
|
||||
xputc(c); continue;
|
||||
}
|
||||
|
||||
/* Get an argument and put it in numeral */
|
||||
#if _USE_LONGLONG
|
||||
if (f & 8) { /* long long argument? */
|
||||
v = va_arg(arp, _LONGLONG_t);
|
||||
} else {
|
||||
if (f & 4) { /* long argument? */
|
||||
v = (d == 'D') ? (long)va_arg(arp, long) : (long)va_arg(arp, unsigned long);
|
||||
} else { /* int/short/char argument */
|
||||
v = (d == 'D') ? (long)va_arg(arp, int) : (long)va_arg(arp, unsigned int);
|
||||
}
|
||||
}
|
||||
#else
|
||||
if (f & 4) { /* long argument? */
|
||||
v = va_arg(arp, long);
|
||||
} else { /* int/short/char argument */
|
||||
v = (d == 'D') ? (long)va_arg(arp, int) : (long)va_arg(arp, unsigned int);
|
||||
}
|
||||
#endif
|
||||
if (d == 'D' && v < 0) { /* Negative value? */
|
||||
v = 0 - v; f |= 16;
|
||||
}
|
||||
i = 0; vs = v;
|
||||
do {
|
||||
d = (char)(vs % r); vs /= r;
|
||||
if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
|
||||
s[i++] = d + '0';
|
||||
} while (vs != 0 && i < sizeof s);
|
||||
if (f & 16) s[i++] = '-';
|
||||
j = i; d = (f & 1) ? '0' : ' ';
|
||||
while (!(f & 2) && j++ < w) xputc(d);
|
||||
do xputc(s[--i]); while (i != 0);
|
||||
while (j++ < w) xputc(' ');
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void xprintf ( /* Put a formatted string to the default device */
|
||||
const char* fmt, /* Pointer to the format string */
|
||||
... /* Optional arguments */
|
||||
)
|
||||
{
|
||||
va_list arp;
|
||||
|
||||
|
||||
va_start(arp, fmt);
|
||||
xvprintf(fmt, arp);
|
||||
va_end(arp);
|
||||
}
|
||||
|
||||
|
||||
void xsprintf ( /* Put a formatted string to the memory */
|
||||
char* buff, /* Pointer to the output buffer */
|
||||
const char* fmt, /* Pointer to the format string */
|
||||
... /* Optional arguments */
|
||||
)
|
||||
{
|
||||
va_list arp;
|
||||
|
||||
|
||||
outptr = buff; /* Switch destination for memory */
|
||||
|
||||
va_start(arp, fmt);
|
||||
xvprintf(fmt, arp);
|
||||
va_end(arp);
|
||||
|
||||
*outptr = 0; /* Terminate output string with a \0 */
|
||||
outptr = 0; /* Switch destination for device */
|
||||
}
|
||||
|
||||
|
||||
void xfprintf ( /* Put a formatted string to the specified device */
|
||||
void(*func)(unsigned char), /* Pointer to the output function */
|
||||
const char* fmt, /* Pointer to the format string */
|
||||
... /* Optional arguments */
|
||||
)
|
||||
{
|
||||
va_list arp;
|
||||
void (*pf)(unsigned char);
|
||||
|
||||
|
||||
pf = xfunc_out; /* Save current output device */
|
||||
xfunc_out = func; /* Switch output to specified device */
|
||||
|
||||
va_start(arp, fmt);
|
||||
xvprintf(fmt, arp);
|
||||
va_end(arp);
|
||||
|
||||
xfunc_out = pf; /* Restore output device */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------*/
|
||||
/* Dump a line of binary dump */
|
||||
/*----------------------------------------------*/
|
||||
|
||||
void put_dump (
|
||||
const void* buff, /* Pointer to the array to be dumped */
|
||||
unsigned long addr, /* Heading address value */
|
||||
int len, /* Number of items to be dumped */
|
||||
int width /* Size of the items (DF_CHAR, DF_SHORT, DF_LONG) */
|
||||
)
|
||||
{
|
||||
int i;
|
||||
const unsigned char *bp;
|
||||
const unsigned short *sp;
|
||||
const unsigned long *lp;
|
||||
|
||||
|
||||
xprintf("%08lX ", addr); /* address */
|
||||
|
||||
switch (width) {
|
||||
case DW_CHAR:
|
||||
bp = buff;
|
||||
for (i = 0; i < len; i++) /* Hexdecimal dump */
|
||||
xprintf(" %02X", bp[i]);
|
||||
xputc(' ');
|
||||
for (i = 0; i < len; i++) /* ASCII dump */
|
||||
xputc((unsigned char)((bp[i] >= ' ' && bp[i] <= '~') ? bp[i] : '.'));
|
||||
break;
|
||||
case DW_SHORT:
|
||||
sp = buff;
|
||||
do /* Hexdecimal dump */
|
||||
xprintf(" %04X", *sp++);
|
||||
while (--len);
|
||||
break;
|
||||
case DW_LONG:
|
||||
lp = buff;
|
||||
do /* Hexdecimal dump */
|
||||
xprintf(" %08LX", *lp++);
|
||||
while (--len);
|
||||
break;
|
||||
}
|
||||
|
||||
xputc('\n');
|
||||
}
|
||||
|
||||
#endif /* _USE_XFUNC_OUT */
|
||||
|
||||
|
||||
|
||||
#if _USE_XFUNC_IN
|
||||
unsigned char (*xfunc_in)(void); /* Pointer to the input stream */
|
||||
|
||||
/*----------------------------------------------*/
|
||||
/* Get a line from the input */
|
||||
/*----------------------------------------------*/
|
||||
|
||||
int xgets ( /* 0:End of stream, 1:A line arrived */
|
||||
char* buff, /* Pointer to the buffer */
|
||||
int len /* Buffer length */
|
||||
)
|
||||
{
|
||||
int c, i;
|
||||
|
||||
|
||||
if (!xfunc_in) return 0; /* No input function specified */
|
||||
|
||||
i = 0;
|
||||
for (;;) {
|
||||
c = xfunc_in(); /* Get a char from the incoming stream */
|
||||
if (!c) return 0; /* End of stream? */
|
||||
if (c == '\r') break; /* End of line? */
|
||||
if (c == '\b' && i) { /* Back space? */
|
||||
i--;
|
||||
if (_LINE_ECHO) xputc((unsigned char)c);
|
||||
continue;
|
||||
}
|
||||
if (c >= ' ' && i < len - 1) { /* Visible chars */
|
||||
buff[i++] = c;
|
||||
if (_LINE_ECHO) xputc((unsigned char)c);
|
||||
}
|
||||
}
|
||||
buff[i] = 0; /* Terminate with a \0 */
|
||||
if (_LINE_ECHO) xputc('\n');
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int xfgets ( /* 0:End of stream, 1:A line arrived */
|
||||
unsigned char (*func)(void), /* Pointer to the input stream function */
|
||||
char* buff, /* Pointer to the buffer */
|
||||
int len /* Buffer length */
|
||||
)
|
||||
{
|
||||
unsigned char (*pf)(void);
|
||||
int n;
|
||||
|
||||
|
||||
pf = xfunc_in; /* Save current input device */
|
||||
xfunc_in = func; /* Switch input to specified device */
|
||||
n = xgets(buff, len); /* Get a line */
|
||||
xfunc_in = pf; /* Restore input device */
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------*/
|
||||
/* Get a value of the string */
|
||||
/*----------------------------------------------*/
|
||||
/* "123 -5 0x3ff 0b1111 0377 w "
|
||||
^ 1st call returns 123 and next ptr
|
||||
^ 2nd call returns -5 and next ptr
|
||||
^ 3rd call returns 1023 and next ptr
|
||||
^ 4th call returns 15 and next ptr
|
||||
^ 5th call returns 255 and next ptr
|
||||
^ 6th call fails and returns 0
|
||||
*/
|
||||
|
||||
int xatoi ( /* 0:Failed, 1:Successful */
|
||||
char **str, /* Pointer to pointer to the string */
|
||||
long *res /* Pointer to the valiable to store the value */
|
||||
)
|
||||
{
|
||||
unsigned long val;
|
||||
unsigned char c, r, s = 0;
|
||||
|
||||
|
||||
*res = 0;
|
||||
|
||||
while ((c = **str) == ' ') (*str)++; /* Skip leading spaces */
|
||||
|
||||
if (c == '-') { /* negative? */
|
||||
s = 1;
|
||||
c = *(++(*str));
|
||||
}
|
||||
|
||||
if (c == '0') {
|
||||
c = *(++(*str));
|
||||
switch (c) {
|
||||
case 'x': /* hexdecimal */
|
||||
r = 16; c = *(++(*str));
|
||||
break;
|
||||
case 'b': /* binary */
|
||||
r = 2; c = *(++(*str));
|
||||
break;
|
||||
default:
|
||||
if (c <= ' ') return 1; /* single zero */
|
||||
if (c < '0' || c > '9') return 0; /* invalid char */
|
||||
r = 8; /* octal */
|
||||
}
|
||||
} else {
|
||||
if (c < '0' || c > '9') return 0; /* EOL or invalid char */
|
||||
r = 10; /* decimal */
|
||||
}
|
||||
|
||||
val = 0;
|
||||
while (c > ' ') {
|
||||
if (c >= 'a') c -= 0x20;
|
||||
c -= '0';
|
||||
if (c >= 17) {
|
||||
c -= 7;
|
||||
if (c <= 9) return 0; /* invalid char */
|
||||
}
|
||||
if (c >= r) return 0; /* invalid char for current radix */
|
||||
val = val * r + c;
|
||||
c = *(++(*str));
|
||||
}
|
||||
if (s) val = 0 - val; /* apply sign if needed */
|
||||
|
||||
*res = val;
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* _USE_XFUNC_IN */
|
||||
@@ -0,0 +1,49 @@
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Universal string handler for user console interface (C)ChaN, 2012 */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _STRFUNC
|
||||
#define _STRFUNC
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define _USE_XFUNC_OUT 1 /* 1: Use output functions */
|
||||
#define _CR_CRLF 1 /* 1: Convert \n ==> \r\n in the output char */
|
||||
#define _USE_LONGLONG 0 /* 1: Enable long long integer in type "ll". */
|
||||
#define _LONGLONG_t long long /* Platform dependent long long integer type */
|
||||
|
||||
#define _USE_XFUNC_IN 1 /* 1: Use input function */
|
||||
#define _LINE_ECHO 1 /* 1: Echo back input chars in xgets function */
|
||||
|
||||
|
||||
#if _USE_XFUNC_OUT
|
||||
#define xdev_out(func) xfunc_out = (void(*)(unsigned char))(func)
|
||||
extern void (*xfunc_out)(unsigned char);
|
||||
extern void xputc (char c);
|
||||
void xfputc (void (*func)(unsigned char), char c);
|
||||
void xputs (const char* str);
|
||||
void xfputs (void (*func)(unsigned char), const char* str);
|
||||
void xprintf (const char* fmt, ...);
|
||||
void xsprintf (char* buff, const char* fmt, ...);
|
||||
void xfprintf (void (*func)(unsigned char), const char* fmt, ...);
|
||||
void put_dump (const void* buff, unsigned long addr, int len, int width);
|
||||
#define DW_CHAR sizeof(char)
|
||||
#define DW_SHORT sizeof(short)
|
||||
#define DW_LONG sizeof(long)
|
||||
#endif
|
||||
|
||||
#if _USE_XFUNC_IN
|
||||
#define xdev_in(func) xfunc_in = (unsigned char(*)(void))(func)
|
||||
extern unsigned char (*xfunc_in)(void);
|
||||
int xgets (char* buff, int len);
|
||||
int xfgets (unsigned char (*func)(void), char* buff, int len);
|
||||
int xatoi (char** str, long* res);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,145 @@
|
||||
#ifndef ANALOG_REG_H_INCLUDED
|
||||
#define ANALOG_REG_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DAC_CFG_EN18_S 0
|
||||
#define DAC_CFG_EN18_M (1 << DAC_CFG_EN18_S)
|
||||
#define DAC_CFG_RESN_S 1
|
||||
#define DAC_CFG_RESN_M (1 << DAC_CFG_RESN_S)
|
||||
#define DAC_CFG_DIV_S 2
|
||||
#define DAC_CFG_DIV_M (0xFF << DAC_CFG_DIV_S)
|
||||
#define DAC_CFG_DIV(v) (((v) << DAC_CFG_DIV_S) & DAC_CFG_DIV_M)
|
||||
#define DAC_CFG_EXTEN_S 10
|
||||
#define DAC_CFG_EXTEN_M (1 << DAC_CFG_EXTEN_S)
|
||||
#define DAC_EXTPAD_EN_S 11
|
||||
#define DAC_EXTPAD_EN_M (1 << DAC_EXTPAD_EN_S)
|
||||
#define DAC_EMPTY_READ_S 13 //Need New Name
|
||||
#define DAC_EMPTY_READ_M (1 << DAC_EMPTY_READ_S)
|
||||
|
||||
|
||||
|
||||
#define TSENS_CFG_NPD_S 0
|
||||
#define TSENS_CFG_NPD_M (1 << TSENS_CFG_NPD_S)
|
||||
#define TSENS_CFG_NPD_CLK_S 1
|
||||
#define TSENS_CFG_NPD_CLK_M (1 << TSENS_CFG_NPD_CLK_S)
|
||||
#define TSENS_CFG_NRST_S 2
|
||||
#define TSENS_CFG_NRST_M (1 << TSENS_CFG_NRST_S)
|
||||
#define TSENS_CFG_CLK_MUX_S 3
|
||||
#define TSENS_CFG_CLK_MUX_M (0b111 << TSENS_CFG_CLK_MUX_S)
|
||||
#define TSENS_CFG_DIV_S 6
|
||||
#define TSENS_CFG_DIV_M (0x3FF << TSENS_CFG_DIV_S)
|
||||
|
||||
#define TSENS_TRESHOLD_HI_S 0
|
||||
#define TSENS_TRESHOLD_HI_M (0x3FF << TSENS_TRESHOLD_HI_S)
|
||||
#define TSENS_TRESHOLD_LOW_S 10
|
||||
#define TSENS_TRESHOLD_LOW_M (0x3FF << TSENS_TRESHOLD_LOW_S)
|
||||
|
||||
#define TSENS_IRQ_EOC_MASK_S 0
|
||||
#define TSENS_IRQ_EOC_MASK_M (1 << TSENS_IRQ_EOC_MASK_S)
|
||||
#define TSENS_IRQ_HI_MASK_S 1
|
||||
#define TSENS_IRQ_HI_MASK_M (1 << TSENS_IRQ_HI_MASK_S)
|
||||
#define TSENS_IRQ_LOW_MASK_S 2
|
||||
#define TSENS_IRQ_LOW_MASK_M (1 << TSENS_IRQ_LOW_MASK_S)
|
||||
#define TSENS_IRQ_EOC_IRQ_S 3
|
||||
#define TSENS_IRQ_EOC_IRQ_M (1 << TSENS_IRQ_EOC_IRQ_S)
|
||||
#define TSENS_IRQ_HI_IRQ_S 4
|
||||
#define TSENS_IRQ_HI_IRQ_M (1 << TSENS_IRQ_HI_IRQ_S)
|
||||
#define TSENS_IRQ_LOW_IRQ_S 5
|
||||
#define TSENS_IRQ_LOW_IRQ_M (1 << TSENS_IRQ_LOW_IRQ_S)
|
||||
|
||||
#define TSENS_CLEAR_IRQ_EOC_CLEAR_S 0
|
||||
#define TSENS_CLEAR_IRQ_EOC_CLEAR_M (1 << TSENS_CLEAR_IRQ_EOC_CLEAR_S)
|
||||
#define TSENS_CLEAR_IRQ_HI_CLEAR_S 1
|
||||
#define TSENS_CLEAR_IRQ_HI_CLEAR_M (1 << TSENS_CLEAR_IRQ_HI_CLEAR_S)
|
||||
#define TSENS_CLEAR_IRQ_LOW_CLEAR_S 2
|
||||
#define TSENS_CLEAR_IRQ_LOW_CLEAR_M (1 << TSENS_CLEAR_IRQ_LOW_CLEAR_S)
|
||||
|
||||
#define TSENS_VALUE_EOC_S 10
|
||||
#define TSENS_VALUE_EOC_M (1 << TSENS_VALUE_EOC_S)
|
||||
#define TSENS_VALUE_VALUE_S 0
|
||||
#define TSENS_VALUE_VALUE_M (0x3FF << TSENS_VALUE_VALUE_S)
|
||||
#define TSENS_CELSIUS_TO_VALUE(i) (40960*100/(((6406600-93*((int)(i)*100+27315))*100)/((int)(i)*100+27315))) // (uint32_t)(4096/((10.3*622)/(i+273.15)-10.3 +1))
|
||||
#define TSENS_VALUE_TO_CELSIUS(v) ((640660*(uint32_t)(v))/(40960+93*(uint32_t)(v))*10-27315) // Значение температуры в 100 раз больше
|
||||
|
||||
|
||||
#define ADC_CONFIG_EN_S 0
|
||||
#define ADC_CONFIG_EN_M (1 << ADC_CONFIG_EN_S)
|
||||
#define ADC_CONFIG_RESETN_S 1
|
||||
#define ADC_CONFIG_RESETN_M (1 << ADC_CONFIG_RESETN_S)
|
||||
#define ADC_CONFIG_EXTREF_S 2
|
||||
#define ADC_CONFIG_EXTREF_M (1 << ADC_CONFIG_EXTREF_S)
|
||||
#define ADC_CONFIG_EXTPAD_EN_S 3
|
||||
#define ADC_CONFIG_EXTPAD_EN_M (1 << ADC_CONFIG_EXTPAD_EN_S)
|
||||
#define ADC_CONFIG_SEL_S 4
|
||||
#define ADC_CONFIG_SEL_M (0b111 << ADC_CONFIG_SEL_S)
|
||||
#define ADC_CONFIG_SAH_TIME_S 8
|
||||
#define ADC_CONFIG_SAH_TIME_M (0x3F << ADC_CONFIG_SAH_TIME_S)
|
||||
|
||||
#define REF_CLB_VCOEF_S 0
|
||||
#define REF_CLB_VCOEF_M (0xF << REF_CLB_VCOEF_S)
|
||||
#define REF_CLB_ICOEF_S 4
|
||||
#define REF_CLB_ICOEF_M (0xF << REF_CLB_ICOEF_S)
|
||||
#define REF_CLB_EN_S 8
|
||||
#define REF_CLB_EN_M (1 << REF_CLB_EN_S)
|
||||
|
||||
#define TEST_DIG_MUX_COV_LDO_M (0 << 9)
|
||||
#define TEST_DIG_MUX_BATON_M (1 << 9)
|
||||
#define TEST_DIG_MUX_BOR_M (2 << 9)
|
||||
#define TEST_DIG_MUX_PGL_BU_M (3 << 9)
|
||||
#define TEST_DIG_MUX_POR_M (4 << 9)
|
||||
#define TEST_DIG_MUX_BGO_M (5 << 9)
|
||||
#define TEST_DIG_MUX_PGL_M (6 << 9)
|
||||
|
||||
#define TEST_DIG_MUX_OSC_CLK32M_M (12 << 9)
|
||||
#define TEST_DIG_MUX_OSC_CLK32K_M (13 << 9)
|
||||
#define TEST_DIG_MUX_RC_CLK32M_M (14 << 9)
|
||||
#define TEST_DIG_MUX_RC_CLK32K_M (15 << 9)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CFG;
|
||||
volatile uint32_t VALUE;
|
||||
} DAC_TypeDef;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile DAC_TypeDef DAC0;
|
||||
volatile DAC_TypeDef DAC1;
|
||||
volatile uint32_t PVD_DPF_VALUE;
|
||||
volatile uint32_t PVD_CONFIG;
|
||||
volatile uint32_t PVD_STATUS;
|
||||
volatile uint32_t TSENS_CFG;
|
||||
volatile uint32_t TSENS_THRESHOLD;
|
||||
volatile uint32_t TSENS_IRQ;
|
||||
volatile uint32_t TSENS_CLEAR_IRQ;
|
||||
volatile uint32_t TSENS_VALUE;
|
||||
volatile uint32_t TSENS_SINGLE;
|
||||
volatile uint32_t TSENS_CONTINUOUS;
|
||||
volatile uint32_t REFV_CONFIG;
|
||||
volatile uint32_t ADC_CONFIG;
|
||||
volatile uint32_t ADC_CONTINUOUS;
|
||||
volatile uint32_t ADC_SINGLE;
|
||||
volatile uint32_t ADC_VALID;
|
||||
volatile uint32_t ADC_VALUE;
|
||||
volatile uint32_t TEST_MUX;
|
||||
|
||||
|
||||
} ANALOG_REG_TypeDef;
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // ANALOG_REG_H_INCLUDED
|
||||
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
#ifndef BOOT_MANAGER_H_INCLUDED
|
||||
#define BOOT_MANAGER_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BOOT_EEPROM 0
|
||||
#define BOOT_RAM 1
|
||||
#define BOOT_SPIFI 2
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t BOOT;
|
||||
} BOOT_MANAGER_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,57 @@
|
||||
#ifndef CRC_H_INCLUDED
|
||||
#define CRC_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CRC_DATA 0x00
|
||||
#define CRC_POLY 0x04
|
||||
#define CRC_CTRL 0x08
|
||||
|
||||
#define CRC_CTRL_TOT_S 30
|
||||
#define CRC_CTRL_TOT_M (3 << CRC_CTRL_TOT_S)
|
||||
#define CRC_CTRL_TOT_NONE_M (0 << CRC_CTRL_TOT_S)
|
||||
#define CRC_CTRL_TOT_BITS_M (1 << CRC_CTRL_TOT_S)
|
||||
#define CRC_CTRL_TOT_BITS_BYTES_M (2 << CRC_CTRL_TOT_S)
|
||||
#define CRC_CTRL_TOT_BYTES_M (3 << CRC_CTRL_TOT_S)
|
||||
|
||||
//
|
||||
#define CRC_CTRL_TOTR_S 28
|
||||
#define CRC_CTRL_TOTR_M (3 << CRC_CTRL_TOTR_S)
|
||||
#define CRC_CTRL_TOTR_NONE_M (0 << CRC_CTRL_TOTR_S)
|
||||
#define CRC_CTRL_TOTR_BITS_M (1 << CRC_CTRL_TOTR_S)
|
||||
#define CRC_CTRL_TOTR_BITS_BYTES_M (2 << CRC_CTRL_TOTR_S)
|
||||
#define CRC_CTRL_TOTR_BYTES_M (3 << CRC_CTRL_TOTR_S)
|
||||
//
|
||||
#define CRC_CTRL_FXOR_S 26
|
||||
#define CRC_CTRL_FXOR_M (1 << CRC_CTRL_FXOR_S)
|
||||
#define CRC_CTRL_WAS_S 25
|
||||
#define CRC_CTRL_WAS_M (1 << CRC_CTRL_WAS_S)
|
||||
//
|
||||
#define CRC_CTRL_BUSY_S 0
|
||||
#define CRC_CTRL_BUSY_M (1 << CRC_CTRL_BUSY_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
volatile uint8_t DATA8;
|
||||
volatile uint16_t DATA16;
|
||||
volatile uint32_t DATA32;
|
||||
};
|
||||
volatile uint32_t POLY;
|
||||
volatile uint32_t CTRL;
|
||||
} CRC_TypeDef;
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CRC_H_INCLUDED
|
||||
@@ -0,0 +1,57 @@
|
||||
#ifndef CRYPTO_H_INCLUDED
|
||||
#define CRYPTO_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CRYPTO_CONFIG_DECODE_S 0
|
||||
#define CRYPTO_CONFIG_ENCODE_M (0 << CRYPTO_CONFIG_DECODE_S)
|
||||
#define CRYPTO_CONFIG_DECODE_M (1 << CRYPTO_CONFIG_DECODE_S)
|
||||
#define CRYPTO_CONFIG_CORE_SEL_S 1
|
||||
#define CRYPTO_CONFIG_CORE_SEL_M (0X3 << CRYPTO_CONFIG_CORE_SEL_S)
|
||||
#define CRYPTO_CONFIG_CORE_SEL_KUZNECHIK_M (0X0 << CRYPTO_CONFIG_CORE_SEL_S)
|
||||
#define CRYPTO_CONFIG_CORE_SEL_MAGMA_M (0X1 << CRYPTO_CONFIG_CORE_SEL_S)
|
||||
#define CRYPTO_CONFIG_CORE_SEL_AES_M (0X2 << CRYPTO_CONFIG_CORE_SEL_S)
|
||||
#define CRYPTO_CONFIG_MODE_SEL_S 3
|
||||
#define CRYPTO_CONFIG_MODE_SEL_M (0X3 << CRYPTO_CONFIG_MODE_SEL_S)
|
||||
#define CRYPTO_CONFIG_MODE_SEL_ECB_M (0X0 << CRYPTO_CONFIG_MODE_SEL_S)
|
||||
#define CRYPTO_CONFIG_MODE_SEL_CBC_M (0X1 << CRYPTO_CONFIG_MODE_SEL_S)
|
||||
#define CRYPTO_CONFIG_MODE_SEL_CTR_M (0X2 << CRYPTO_CONFIG_MODE_SEL_S)
|
||||
#define CRYPTO_CONFIG_SWAP_MODE_S 5
|
||||
#define CRYPTO_CONFIG_SWAP_MODE_M (0X3 << CRYPTO_CONFIG_SWAP_MODE_S)
|
||||
#define CRYPTO_CONFIG_SWAP_MODE_NONE_M (0X0 << CRYPTO_CONFIG_SWAP_MODE_S)
|
||||
#define CRYPTO_CONFIG_SWAP_MODE_HALF_WORD_M (0X1 << CRYPTO_CONFIG_SWAP_MODE_S)
|
||||
#define CRYPTO_CONFIG_SWAP_MODE_BYTE_M (0X2 << CRYPTO_CONFIG_SWAP_MODE_S)
|
||||
#define CRYPTO_CONFIG_SWAP_MODE_BIT_M (0X3 << CRYPTO_CONFIG_SWAP_MODE_S)
|
||||
#define CRYPTO_CONFIG_ORDER_MODE_S 7
|
||||
#define CRYPTO_CONFIG_ORDER_MODE_M (1 << CRYPTO_CONFIG_ORDER_MODE_S)
|
||||
#define CRYPTO_CONFIG_ORDER_MODE_LSW_M (0 << CRYPTO_CONFIG_ORDER_MODE_S)
|
||||
#define CRYPTO_CONFIG_ORDER_MODE_MSW_M (1 << CRYPTO_CONFIG_ORDER_MODE_S)
|
||||
#define CRYPTO_CONFIG_C_RESET_S 8
|
||||
#define CRYPTO_CONFIG_C_RESET_M (1 << CRYPTO_CONFIG_C_RESET_S)
|
||||
#define CRYPTO_CONFIG_READY_S 9
|
||||
#define CRYPTO_CONFIG_READY_M (1 << CRYPTO_CONFIG_READY_S)
|
||||
#define CRYPTO_CONFIG_WRITE_STATUS_S 10
|
||||
#define CRYPTO_CONFIG_WRITE_STATUS_M (1 << CRYPTO_CONFIG_WRITE_STATUS_S)
|
||||
#define CRYPTO_CONFIG_READ_STATUS_S 11
|
||||
#define CRYPTO_CONFIG_READ_STATUS_M (1 << CRYPTO_CONFIG_READ_STATUS_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t BLOCK;
|
||||
volatile uint32_t KEY;
|
||||
volatile uint32_t INIT;
|
||||
volatile uint32_t CONFIG;
|
||||
} CRYPTO_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CRYPTO_H_INCLUDED
|
||||
@@ -0,0 +1,117 @@
|
||||
#ifndef DMA_MC_H_INCLUDED
|
||||
#define DMA_MC_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DMA_CHANNEL_COUNT 4
|
||||
|
||||
|
||||
#define DMA_CH_CFG_ENABLE_S 0
|
||||
#define DMA_CH_CFG_ENABLE_M (1 << DMA_CH_CFG_ENABLE_S)
|
||||
#define DMA_CH_CFG_DISABLE_M (0 << DMA_CH_CFG_ENABLE_S)
|
||||
|
||||
#define DMA_CH_CFG_PRIOR_S 1
|
||||
#define DMA_CH_CFG_PRIOR_M (0X3 << DMA_CH_CFG_PRIOR_S)
|
||||
#define DMA_CH_CFG_PRIOR_LOW_M (0B00 << DMA_CH_CFG_PRIOR_S)
|
||||
#define DMA_CH_CFG_PRIOR_MEDIUM_M (0B01 << DMA_CH_CFG_PRIOR_S)
|
||||
#define DMA_CH_CFG_PRIOR_HIGH_M (0B10 << DMA_CH_CFG_PRIOR_S)
|
||||
#define DMA_CH_CFG_PRIOR_VERY_HIGH_M (0B11 << DMA_CH_CFG_PRIOR_S)
|
||||
|
||||
#define DMA_CH_CFG_READ_MODE_S 3
|
||||
#define DMA_CH_CFG_READ_MODE_MEMORY_M (1 << DMA_CH_CFG_READ_MODE_S)
|
||||
#define DMA_CH_CFG_READ_MODE_PERIPHERY_M (0 << DMA_CH_CFG_READ_MODE_S)
|
||||
|
||||
#define DMA_CH_CFG_WRITE_MODE_S 4
|
||||
#define DMA_CH_CFG_WRITE_MODE_MEMORY_M (1 << DMA_CH_CFG_WRITE_MODE_S)
|
||||
#define DMA_CH_CFG_WRITE_MODE_PERIPHERY_M (0 << DMA_CH_CFG_WRITE_MODE_S)
|
||||
|
||||
#define DMA_CH_CFG_READ_INCREMENT_S 5
|
||||
#define DMA_CH_CFG_READ_INCREMENT_M (1 << DMA_CH_CFG_READ_INCREMENT_S)
|
||||
#define DMA_CH_CFG_READ_NO_INCREMENT_M (0 << DMA_CH_CFG_READ_INCREMENT_S)
|
||||
|
||||
#define DMA_CH_CFG_WRITE_INCREMENT_S 6
|
||||
#define DMA_CH_CFG_WRITE_INCREMENT_M (1 << DMA_CH_CFG_WRITE_INCREMENT_S)
|
||||
#define DMA_CH_CFG_WRITE_NO_INCREMENT_M (0 << DMA_CH_CFG_WRITE_INCREMENT_S)
|
||||
|
||||
#define DMA_CH_CFG_READ_SIZE_S 7
|
||||
#define DMA_CH_CFG_READ_SIZE_BYTE_M (0B00 << DMA_CH_CFG_READ_SIZE_S) // байт
|
||||
#define DMA_CH_CFG_READ_SIZE_2BYTE_M (0B01 << DMA_CH_CFG_READ_SIZE_S) // полуслово
|
||||
#define DMA_CH_CFG_READ_SIZE_4BYTE_M (0B10 << DMA_CH_CFG_READ_SIZE_S) // слово
|
||||
#define DMA_CH_CFG_READ_SIZE_REZ_M (0B11 << DMA_CH_CFG_READ_SIZE_S) // резерв
|
||||
|
||||
#define DMA_CH_CFG_WRITE_SIZE_S 9
|
||||
#define DMA_CH_CFG_WRITE_SIZE_BYTE_M (0B00 << DMA_CH_CFG_WRITE_SIZE_S) // байт
|
||||
#define DMA_CH_CFG_WRITE_SIZE_2BYTE_M (0B01 << DMA_CH_CFG_WRITE_SIZE_S) // полуслово
|
||||
#define DMA_CH_CFG_WRITE_SIZE_4BYTE_M (0B10 << DMA_CH_CFG_WRITE_SIZE_S) // слово
|
||||
#define DMA_CH_CFG_WRITE_SIZE_REZ_M (0B11 << DMA_CH_CFG_WRITE_SIZE_S) // резерв
|
||||
|
||||
#define DMA_CH_CFG_READ_BURST_SIZE_S 11 //Кол-во байт пакетной передачи: 2^Read_burst_size
|
||||
#define DMA_CH_CFG_WRITE_BURST_SIZE_S 14 //Кол-во байт пакетной передачи: 2^Write_burst_size
|
||||
|
||||
#define DMA_CH_CFG_READ_REQUETS_S 17 // выбор канала чтения
|
||||
#define DMA_CH_CFG_READ_REQUETS_M (0xF << DMA_CH_CFG_READ_REQUETS_S)
|
||||
#define DMA_CH_CFG_READ_REQUETS(v) (((v) << DMA_CH_CFG_READ_REQUETS_S) & DMA_CH_CFG_READ_REQUETS_M)
|
||||
|
||||
#define DMA_CH_CFG_WRITE_REQUETS_S 21 // выбор канала записи
|
||||
#define DMA_CH_CFG_WRITE_REQUETS_M (0xF << DMA_CH_CFG_WRITE_REQUETS_S)
|
||||
#define DMA_CH_CFG_WRITE_REQUETS(v) (((v) << DMA_CH_CFG_WRITE_REQUETS_S) & DMA_CH_CFG_WRITE_REQUETS_M)
|
||||
|
||||
|
||||
#define DMA_CH_CFG_READ_ACK_EN_S 25
|
||||
#define DMA_CH_CFG_READ_ACK_EN_M (1 << DMA_CH_CFG_READ_ACK_EN_S)
|
||||
#define DMA_CH_CFG_WRITE_ACK_EN_S 26
|
||||
#define DMA_CH_CFG_WRITE_ACK_EN_M (1 << DMA_CH_CFG_WRITE_ACK_EN_S)
|
||||
#define DMA_CH_CFG_IRQ_EN_S 27
|
||||
#define DMA_CH_CFG_IRQ_EN_M (1 << DMA_CH_CFG_IRQ_EN_S)
|
||||
|
||||
#define DMA_CHANNEL_M ((1 << DMA_CHANNEL_COUNT) - 1)
|
||||
|
||||
#define DMA_STATUS_READY_S 0
|
||||
#define DMA_STATUS_READY_M (DMA_CHANNEL_M << DMA_STATUS_READY_S)
|
||||
#define DMA_STATUS_READY(i) ((1 << (DMA_STATUS_READY_S + (i))) & DMA_STATUS_READY_M)
|
||||
#define DMA_STATUS_CHANNEL_IRQ_S 1 * DMA_CHANNEL_COUNT
|
||||
#define DMA_STATUS_CHANNEL_IRQ_M (DMA_CHANNEL_M << DMA_STATUS_CHANNEL_IRQ_S)
|
||||
#define DMA_STATUS_CHANNEL_BUS_ERROR_S 2 * DMA_CHANNEL_COUNT
|
||||
#define DMA_STATUS_CHANNEL_BUS_ERROR_M (DMA_CHANNEL_M << DMA_STATUS_CHANNEL_BUS_ERROR_S)
|
||||
|
||||
#define DMA_CONFIG_CLEAR_LOCAL_IRQ_S 0
|
||||
#define DMA_CONFIG_CLEAR_LOCAL_IRQ_M (DMA_CHANNEL_M << DMA_CONFIG_CLEAR_LOCAL_IRQ_S)
|
||||
#define DMA_CONFIG_CLEAR_LOCAL_IRQ(i) ((1 << (DMA_CONTROL_CLEAR_LOCAL_IRQ_S + (i))) & DMA_CONTROL_CLEAR_LOCAL_IRQ_M)
|
||||
#define DMA_CONFIG_CLEAR_GLOBAL_IRQ_S (DMA_CHANNEL_COUNT + 0)
|
||||
#define DMA_CONFIG_CLEAR_GLOBAL_IRQ_M (1 << DMA_CONFIG_CLEAR_GLOBAL_IRQ_S)
|
||||
#define DMA_CONFIG_CLEAR_ERROR_IRQ_S (DMA_CHANNEL_COUNT + 1)
|
||||
#define DMA_CONFIG_CLEAR_ERROR_IRQ_M (1 << DMA_CONFIG_CLEAR_ERROR_IRQ_S)
|
||||
#define DMA_CONFIG_GLOBAL_IRQ_ENA_S (DMA_CHANNEL_COUNT + 2)
|
||||
#define DMA_CONFIG_GLOBAL_IRQ_ENA_M (1 << DMA_CONFIG_GLOBAL_IRQ_ENA_S)
|
||||
#define DMA_CONFIG_ERROR_IRQ_ENA_S (DMA_CHANNEL_COUNT + 3)
|
||||
#define DMA_CONFIG_ERROR_IRQ_ENA_M (1 << DMA_CONFIG_ERROR_IRQ_ENA_S)
|
||||
#define DMA_CONFIG_CURRENT_VALUE_S (DMA_CHANNEL_COUNT + 4)
|
||||
#define DMA_CONFIG_CURRENT_VALUE_M (1 << DMA_CONFIG_CURRENT_VALUE_S)
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
volatile uint32_t DST; // 0x00
|
||||
volatile uint32_t SRC; // 0x04
|
||||
volatile uint32_t LEN; // 0x08
|
||||
volatile uint32_t CFG; // 0x0c
|
||||
} DMA_CHANNEL_TypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
DMA_CHANNEL_TypeDef CHANNELS[DMA_CHANNEL_COUNT];
|
||||
volatile uint32_t CONFIG_STATUS; // 0x40
|
||||
} DMA_CONFIG_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif //
|
||||
@@ -0,0 +1,120 @@
|
||||
#ifndef EEPROM_H_INCLUDED
|
||||
#define EEPROM_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------
|
||||
// EEPROM register fields
|
||||
//--------------------------
|
||||
|
||||
//EEDAT
|
||||
//EEA
|
||||
#define EEPROM_EEA_ADDR_S 2
|
||||
#define EEPROM_EEA_ADDR_M (0b7FF << EEPROM_EEA_ADDR_S)
|
||||
#define EEPROM_EEA_ADDR(v) (((v) << EEPROM_EEA_ADDR_S) & EEPROM_EEA_ADDR_M)
|
||||
//EECON
|
||||
#define EEPROM_EECON_EX_S 0
|
||||
#define EEPROM_EECON_EX_M (1 << EEPROM_EECON_EX_S)
|
||||
#define EEPROM_EECON_OP_S 1
|
||||
#define EEPROM_EECON_OP_M (0b11 << EEPROM_EECON_OP_S)
|
||||
#define EEPROM_EECON_OP(v) (((v) << EEPROM_EECON_OP_S) & EEPROM_EECON_OP_M)
|
||||
#define EEPROM_EECON_WRBEH_S 3
|
||||
#define EEPROM_EECON_WRBEH_M (0b11 << EEPROM_EECON_WRBEH_S)
|
||||
#define EEPROM_EECON_WRBEH(v) (((v) << EEPROM_EECON_WRBEH_S) & EEPROM_EECON_WRBEH_M)
|
||||
#define EEPROM_EECON_APBNWS_S 5
|
||||
#define EEPROM_EECON_APBNWS_M (1 << EEPROM_EECON_APBNWS_S)
|
||||
#define EEPROM_EECON_DISECC_S 6
|
||||
#define EEPROM_EECON_DISECC_M (1 << EEPROM_EECON_DISECC_S)
|
||||
#define EEPROM_EECON_BWE_S 7
|
||||
#define EEPROM_EECON_BWE_M (1 << EEPROM_EECON_BWE_S)
|
||||
#define EEPROM_EECON_IESERR_S 8
|
||||
#define EEPROM_EECON_IESERR_M (1 << EEPROM_EECON_IESERR_S)
|
||||
//EESTA
|
||||
#define EEPROM_EESTA_BSY_S 0
|
||||
#define EEPROM_EESTA_BSY_M (1 << EEPROM_EESTA_BSY_S)
|
||||
#define EEPROM_EESTA_SERR_S 1
|
||||
#define EEPROM_EESTA_SERR_M (1 << EEPROM_EESTA_SERR_S)
|
||||
//EERB
|
||||
#define EEPROM_EERB_CORRECT_S 0
|
||||
#define EEPROM_EERB_CORRECT_M (0b111111 << EEPROM_EERB_CORRECT_S)
|
||||
//EEADJ
|
||||
#define EEPROM_EEADJ_OSCX2_S 0
|
||||
#define EEPROM_EEADJ_OSCX2_M (1 << EEPROM_EEADJ_OSCX2_S)
|
||||
#define EEPROM_EEADJ_HIVCTL_S 0
|
||||
#define EEPROM_EEADJ_HIVCTL_M (0b111 << EEPROM_EEADJ_HIVCTL_S)
|
||||
#define EEPROM_EEADJ_PLUSIMIX_S 0
|
||||
#define EEPROM_EEADJ_PLUSIMIX_M (1 << EEPROM_EEADJ_PLUSIMIX_S)
|
||||
#define EEPROM_EEADJ_VBOOSTCTL_S 0
|
||||
#define EEPROM_EEADJ_VBOOSTCTL_M (0b11 << EEPROM_EEADJ_VBOOSTCTL_S)
|
||||
#define EEPROM_EEADJ_MINUSIMIX_S 0
|
||||
#define EEPROM_EEADJ_MINUSIMIX_M (1 << EEPROM_EEADJ_MINUSIMIX_S)
|
||||
#define EEPROM_EEADJ_DUMMYCTL_S 0
|
||||
#define EEPROM_EEADJ_DUMMYCTL_M (0b11 << EEPROM_EEADJ_DUMMYCTL_S)
|
||||
#define EEPROM_EEADJ_VBGCTL_S 0
|
||||
#define EEPROM_EEADJ_VBGCTL_M (0b111 << EEPROM_EEADJ_VBGCTL_S)
|
||||
#define EEPROM_EEADJ_REFCTL_S 0
|
||||
#define EEPROM_EEADJ_REFCTL_M (0b111 << EEPROM_EEADJ_REFCTL_S)
|
||||
#define EEPROM_EEADJ_VCGCTL_S 0
|
||||
#define EEPROM_EEADJ_VCGCTL_M (0b111 << EEPROM_EEADJ_VCGCTL_S)
|
||||
#define EEPROM_EEADJ_CGSTRICT_S 0
|
||||
#define EEPROM_EEADJ_CGSTRICT_M (1 << EEPROM_EEADJ_CGSTRICT_S)
|
||||
#define EEPROM_EEADJ_VPPCTL_S 0
|
||||
#define EEPROM_EEADJ_VPPCTL_M (0b11 << EEPROM_EEADJ_VPPCTL_S)
|
||||
#define EEPROM_EEADJ_STOPEE_S 0
|
||||
#define EEPROM_EEADJ_STOPEE_M (1 << EEPROM_EEADJ_STOPEE_S)
|
||||
#define EEPROM_EEADJ_IDDQEN_S 0
|
||||
#define EEPROM_EEADJ_IDDQEN_M (1 << EEPROM_EEADJ_IDDQEN_S)
|
||||
//NCYCRL
|
||||
#define EEPROM_NCYCRL_N_LD_S 0
|
||||
#define EEPROM_NCYCRL_N_LD_M (0xFF << EEPROM_NCYCRL_N_LD_S)
|
||||
#define EEPROM_NCYCRL_N_R_1_S 8
|
||||
#define EEPROM_NCYCRL_N_R_1_M (0xFF << EEPROM_NCYCRL_N_R_1_S)
|
||||
#define EEPROM_NCYCRL_N_R_2_S 16
|
||||
#define EEPROM_NCYCRL_N_R_2_M (0xFF << EEPROM_NCYCRL_N_R_2_S)
|
||||
//NCYCEP1
|
||||
#define EEPROM_NCYCEP1_N_EP_1_S 0
|
||||
#define EEPROM_NCYCEP1_N_EP_1_M (0x3FFFF << EEPROM_NCYCEP1_N_EP_1_S)
|
||||
//NCYCEP2
|
||||
#define EEPROM_NCYCEP2_N_EP_2_S 0
|
||||
#define EEPROM_NCYCEP2_N_EP_2_M (0x7FF << EEPROM_NCYCEP2_N_EP_2_S)
|
||||
|
||||
//--------------------------
|
||||
// EEPROM codes
|
||||
//--------------------------
|
||||
|
||||
#define EEPROM_EECON_OP_RD 0
|
||||
#define EEPROM_EECON_OP_ER 1
|
||||
#define EEPROM_EECON_OP_PR 2
|
||||
#define EEPROM_WRBEH_SINGLE 0
|
||||
#define EEPROM_WRBEH_EVEN 1
|
||||
#define EEPROM_WRBEH_ODD 2
|
||||
#define EEPROM_WRBEH_GLOB 3
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t EEDAT;
|
||||
volatile uint32_t EEA;
|
||||
volatile uint32_t EECON;
|
||||
volatile uint32_t EESTA;
|
||||
volatile uint32_t EERB;
|
||||
volatile uint32_t EEADJ;
|
||||
volatile uint32_t NCYCRL;
|
||||
volatile uint32_t NCYCEP1;
|
||||
volatile uint32_t NCYCEP2;
|
||||
|
||||
} EEPROM_REGS_TypeDef;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // EEPROM_H_INCLUDED
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
#ifndef EPIC_H_INCLUDED
|
||||
#define EPIC_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EPIC_MASK_EDGE_SET 0x00
|
||||
#define EPIC_MASK_EDGE_CLEAR 0x04
|
||||
#define EPIC_MASK_LEVEL_SET 0x08
|
||||
#define EPIC_MASK_LEVEL_CLEAR 0x0C
|
||||
#define EPIC_CLEAR 0x18
|
||||
#define EPIC_STATUS 0x1C
|
||||
#define EPIC_RAW_STATUS 0x20
|
||||
|
||||
// Линии прерываний
|
||||
#define EPIC_LINE_TIMER32_0_S 0
|
||||
#define EPIC_LINE_UART_0_S 1
|
||||
#define EPIC_LINE_UART_1_S 2
|
||||
#define EPIC_LINE_SPI_0_S 3
|
||||
#define EPIC_LINE_SPI_1_S 4
|
||||
#define EPIC_LINE_GPIO_IRQ_S 5
|
||||
#define EPIC_LINE_I2C_0_S 6
|
||||
#define EPIC_LINE_I2C_1_S 7
|
||||
#define EPIC_LINE_WDT_S 8
|
||||
#define EPIC_LINE_TIMER16_0_S 9
|
||||
#define EPIC_LINE_TIMER16_1_S 10
|
||||
#define EPIC_LINE_TIMER16_2_S 11
|
||||
#define EPIC_LINE_TIMER32_1_S 12
|
||||
#define EPIC_LINE_TIMER32_2_S 13
|
||||
#define EPIC_LINE_SPIFI_S 14
|
||||
#define EPIC_LINE_RTC_S 15
|
||||
#define EPIC_LINE_EEPROM_S 16
|
||||
#define EPIC_LINE_WDT_DOM3_S 17
|
||||
#define EPIC_LINE_WDT_SPIFI_S 18
|
||||
#define EPIC_LINE_WDT_EEPROM_S 19
|
||||
#define EPIC_LINE_DMA_S 20
|
||||
#define EPIC_LINE_FREQ_MON_S 21
|
||||
#define EPIC_LINE_PVD_AVCC_UNDER_S 22
|
||||
#define EPIC_LINE_PVD_AVCC_OVER_S 23
|
||||
#define EPIC_LINE_PVD_VCC_UNDER_S 24
|
||||
#define EPIC_LINE_PVD_VCC_OVER_S 25
|
||||
#define EPIC_LINE_BATTERY_NON_GOOD_S 26
|
||||
#define EPIC_LINE_BOR_S 27
|
||||
#define EPIC_LINE_TSENS_S 28
|
||||
#define EPIC_LINE_ADC_S 29
|
||||
#define EPIC_LINE_DAC0_S 30
|
||||
#define EPIC_LINE_DAC1_S 31
|
||||
#define EPIC_LINE_M(interrupt_line) (1 << interrupt_line)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t MASK_EDGE_SET; // 0x00
|
||||
volatile uint32_t MASK_EDGE_CLEAR; // 0x04
|
||||
volatile uint32_t MASK_LEVEL_SET; // 0x08
|
||||
volatile uint32_t MASK_LEVEL_CLEAR; // 0x0C
|
||||
volatile uint32_t reserved[2]; // reserved
|
||||
volatile uint32_t CLEAR; // 0x18
|
||||
volatile uint32_t STATUS; // 0x1C
|
||||
volatile uint32_t RAW_STATUS; // 0x20
|
||||
} EPIC_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // EPIC_H_INCLUDED
|
||||
@@ -0,0 +1,42 @@
|
||||
#ifndef GPIO_H_INCLUDED
|
||||
#define GPIO_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GPIO_STATE 0x00
|
||||
#define GPIO_SET 0x00
|
||||
#define GPIO_CLEAR 0x04
|
||||
#define GPIO_DIRECTION_OUT 0x08
|
||||
#define GPIO_DIRECTION_IN 0x0C
|
||||
#define GPIO_OUTPUT 0x10
|
||||
#define GPIO_CONTROL 0x14
|
||||
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
volatile uint32_t SET;
|
||||
volatile uint32_t STATE;
|
||||
};
|
||||
volatile uint32_t CLEAR;
|
||||
volatile uint32_t DIRECTION_OUT;
|
||||
volatile uint32_t DIRECTION_IN;
|
||||
volatile uint32_t OUTPUT_;
|
||||
volatile uint32_t CONTROL;
|
||||
|
||||
} GPIO_TypeDef;
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,39 @@
|
||||
#ifndef GPIO_IRQ_H_INCLUDED
|
||||
#define GPIO_IRQ_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define GPIO_IRQ_LINE_M(line_num) (1 << (line_num))
|
||||
// LINE_MUX
|
||||
#define GPIO_IRQ_LINE_MUX_M(line_num) (0xF << ((line_num) << 2))
|
||||
#define GPIO_IRQ_LINE_MUX(mux, line_num) (((mux) << ((line_num) << 2)) & GPIO_IRQ_LINE_MUX_M(line_num))
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t STATE;
|
||||
volatile uint32_t LINE_MUX;
|
||||
volatile uint32_t INTERRUPT;
|
||||
volatile uint32_t ENABLE_SET;
|
||||
volatile uint32_t ENABLE_CLEAR;
|
||||
volatile uint32_t EDGE;
|
||||
volatile uint32_t LEVEL;
|
||||
volatile uint32_t LEVEL_SET;
|
||||
volatile uint32_t LEVEL_CLEAR;
|
||||
volatile uint32_t ANY_EDGE_SET;
|
||||
volatile uint32_t ANY_EDGE_CLEAR;
|
||||
volatile uint32_t CLEAR;
|
||||
} GPIO_IRQ_TypeDef;
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,175 @@
|
||||
#ifndef I2C_H_INCLUDED
|
||||
#define I2C_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define I2C_CR1_PE_S 0
|
||||
#define I2C_CR1_PE_M (1 << I2C_CR1_PE_S)
|
||||
#define I2C_CR1_TXIE_S 1
|
||||
#define I2C_CR1_TXIE_M (1 << I2C_CR1_TXIE_S)
|
||||
#define I2C_CR1_RXIE_S 2
|
||||
#define I2C_CR1_RXIE_M (1 << I2C_CR1_RXIE_S)
|
||||
#define I2C_CR1_ADDRIE_S 3
|
||||
#define I2C_CR1_ADDRIE_M (1 << I2C_CR1_ADDRIE_S)
|
||||
#define I2C_CR1_NACKIE_S 4
|
||||
#define I2C_CR1_NACKIE_M (1 << I2C_CR1_NACKIE_S)
|
||||
#define I2C_CR1_STOPIE_S 5
|
||||
#define I2C_CR1_STOPIE_M (1 << I2C_CR1_STOPIE_S)
|
||||
#define I2C_CR1_TCIE_S 6
|
||||
#define I2C_CR1_TCIE_M (1 << I2C_CR1_TCIE_S)
|
||||
#define I2C_CR1_ERRIE_S 7
|
||||
#define I2C_CR1_ERRIE_M (1 << I2C_CR1_ERRIE_S)
|
||||
#define I2C_CR1_DNF_S 8
|
||||
#define I2C_CR1_DNF_M (0xF << I2C_CR1_DNF_S)
|
||||
#define I2C_CR1_DNF(v) (((v) << I2C_CR1_DNF_S) & I2C_CR1_DNF_M)
|
||||
#define I2C_CR1_ANFOFF_S 12
|
||||
#define I2C_CR1_ANFOFF_M (1 << I2C_CR1_ANFOFF_S)
|
||||
//
|
||||
#define I2C_CR1_TXDMAEN_S 14
|
||||
#define I2C_CR1_TXDMAEN_M (1 << I2C_CR1_TXDMAEN_S)
|
||||
#define I2C_CR1_RXDMAEN_S 15
|
||||
#define I2C_CR1_RXDMAEN_M (1 << I2C_CR1_RXDMAEN_S)
|
||||
#define I2C_CR1_SBC_S 16
|
||||
#define I2C_CR1_SBC_M (1 << I2C_CR1_SBC_S)
|
||||
#define I2C_CR1_NOSTRETCH_S 17
|
||||
#define I2C_CR1_NOSTRETCH_M (1 << I2C_CR1_NOSTRETCH_S)
|
||||
//
|
||||
#define I2C_CR1_GCEN_S 19
|
||||
#define I2C_CR1_GCEN_M (1 << I2C_CR1_GCEN_S)
|
||||
|
||||
|
||||
#define I2C_CR2_SADD_S 0
|
||||
#define I2C_CR2_SADD_M (0x3FF << I2C_CR2_SADD_S)
|
||||
#define I2C_CR2_SADD(v) (((v) << I2C_CR2_SADD_S) &I2C_CR2_SADD_M)
|
||||
#define I2C_CR2_RD_WRN_S 10
|
||||
#define I2C_CR2_RD_WRN_M (1 << I2C_CR2_RD_WRN_S)
|
||||
#define I2C_CR2_RD_M (1 << I2C_CR2_RD_WRN_S)
|
||||
#define I2C_CR2_WR_M (0 << I2C_CR2_RD_WRN_S)
|
||||
#define I2C_CR2_ADD10_S 11
|
||||
#define I2C_CR2_ADD10_M (1 << I2C_CR2_ADD10_S)
|
||||
#define I2C_CR2_HEAD10R_S 12
|
||||
#define I2C_CR2_HEAD10R_M (1 << I2C_CR2_HEAD10R_S)
|
||||
#define I2C_CR2_START_S 13
|
||||
#define I2C_CR2_START_M (1 << I2C_CR2_START_S)
|
||||
#define I2C_CR2_STOP_S 14
|
||||
#define I2C_CR2_STOP_M (1 << I2C_CR2_STOP_S)
|
||||
#define I2C_CR2_NACK_S 15
|
||||
#define I2C_CR2_NACK_M (1 << I2C_CR2_NACK_S)
|
||||
#define I2C_CR2_NBYTES_S 16
|
||||
#define I2C_CR2_NBYTES_M (0xFF << I2C_CR2_NBYTES_S)
|
||||
#define I2C_CR2_NBYTES(v) (((v) << I2C_CR2_NBYTES_S) & I2C_CR2_NBYTES_M)
|
||||
#define I2C_CR2_RELOAD_S 24
|
||||
#define I2C_CR2_RELOAD_M (1 << I2C_CR2_RELOAD_S)
|
||||
#define I2C_CR2_AUTOEND_S 25
|
||||
#define I2C_CR2_AUTOEND_M (1 << I2C_CR2_AUTOEND_S)
|
||||
|
||||
|
||||
#define I2C_OAR1_OA1_S 0
|
||||
#define I2C_OAR1_OA1_M (0x3FF << I2C_OAR1_OA1_S)
|
||||
#define I2C_OAR1_OA1MODE_S 10
|
||||
#define I2C_OAR1_OA1MODE_M (1 << I2C_OAR1_OA1MODE_S)
|
||||
//
|
||||
#define I2C_OAR1_OA1EN_S 15
|
||||
#define I2C_OAR1_OA1EN_M (1 << I2C_OAR1_OA1EN_S)
|
||||
|
||||
|
||||
#define I2C_OAR2_OA2_S 1
|
||||
#define I2C_OAR2_OA2_M (0x7F << I2C_OAR2_OA2_S)
|
||||
#define I2C_OAR2_OA2MSK_S 8
|
||||
#define I2C_OAR2_OA2MSK_M (0x7 << I2C_OAR2_OA2MSK_S)
|
||||
//
|
||||
#define I2C_OAR2_OA2EN_S 15
|
||||
#define I2C_OAR2_OA2EN_M (1 << I2C_OAR2_OA2EN_S)
|
||||
|
||||
|
||||
#define I2C_TIMINGR_SCLL_S 0
|
||||
#define I2C_TIMINGR_SCLL_M (0xFF << I2C_TIMINGR_SCLL_S)
|
||||
#define I2C_TIMINGR_SCLL(v) (((v) << I2C_TIMINGR_SCLL_S) & I2C_TIMINGR_SCLL_M)
|
||||
#define I2C_TIMINGR_SCLH_S 8
|
||||
#define I2C_TIMINGR_SCLH_M (0xFF << I2C_TIMINGR_SCLH_S)
|
||||
#define I2C_TIMINGR_SCLH(v) (((v) << I2C_TIMINGR_SCLH_S) & I2C_TIMINGR_SCLH_M)
|
||||
#define I2C_TIMINGR_SDADEL_S 16
|
||||
#define I2C_TIMINGR_SDADEL_M (0xF << I2C_TIMINGR_SDADEL_S)
|
||||
#define I2C_TIMINGR_SDADEL(v) (((v) << I2C_TIMINGR_SDADEL_S) & I2C_TIMINGR_SDADEL_M)
|
||||
#define I2C_TIMINGR_SCLDEL_S 20
|
||||
#define I2C_TIMINGR_SCLDEL_M (0xF << I2C_TIMINGR_SCLDEL_S)
|
||||
#define I2C_TIMINGR_SCLDEL(v) (((v) << I2C_TIMINGR_SCLDEL_S) & I2C_TIMINGR_SCLDEL_M)
|
||||
#define I2C_TIMINGR_PRESC_S 28
|
||||
#define I2C_TIMINGR_PRESC_M (0xF << I2C_TIMINGR_PRESC_S)
|
||||
#define I2C_TIMINGR_PRESC(v) (((v) << I2C_TIMINGR_PRESC_S) & I2C_TIMINGR_PRESC_M)
|
||||
|
||||
|
||||
#define I2C_ISR_TXE_S 0
|
||||
#define I2C_ISR_TXE_M (1 << I2C_ISR_TXE_S)
|
||||
#define I2C_ISR_TXIS_S 1
|
||||
#define I2C_ISR_TXIS_M (1 << I2C_ISR_TXIS_S)
|
||||
#define I2C_ISR_RXNE_S 2
|
||||
#define I2C_ISR_RXNE_M (1 << I2C_ISR_RXNE_S)
|
||||
#define I2C_ISR_ADDR_S 3
|
||||
#define I2C_ISR_ADDR_M (1 << I2C_ISR_ADDR_S)
|
||||
#define I2C_ISR_NACKF_S 4
|
||||
#define I2C_ISR_NACKF_M (1 << I2C_ISR_NACKF_S)
|
||||
#define I2C_ISR_STOPF_S 5
|
||||
#define I2C_ISR_STOPF_M (1 << I2C_ISR_STOPF_S)
|
||||
#define I2C_ISR_TC_S 6
|
||||
#define I2C_ISR_TC_M (1 << I2C_ISR_TC_S)
|
||||
#define I2C_ISR_TCR_S 7
|
||||
#define I2C_ISR_TCR_M (1 << I2C_ISR_TCR_S)
|
||||
#define I2C_ISR_BERR_S 8
|
||||
#define I2C_ISR_BERR_M (1 << I2C_ISR_BERR_S)
|
||||
#define I2C_ISR_ARLO_S 9
|
||||
#define I2C_ISR_ARLO_M (1 << I2C_ISR_ARLO_S)
|
||||
#define I2C_ISR_OVR_S 10
|
||||
#define I2C_ISR_OVR_M (1 << I2C_ISR_OVR_S)
|
||||
//
|
||||
#define I2C_ISR_BUSY_S 15
|
||||
#define I2C_ISR_BUSY_M (1 << I2C_ISR_BUSY_S)
|
||||
#define I2C_ISR_DIR_S 16
|
||||
#define I2C_ISR_DIR_M (1 << I2C_ISR_DIR_S)
|
||||
#define I2C_ISR_ADDCODE_S 17
|
||||
#define I2C_ISR_ADDCODE_M (0x7F << I2C_ISR_ADDCODE_S)
|
||||
|
||||
|
||||
#define I2C_ICR_ADDRCF_S 3
|
||||
#define I2C_ICR_ADDRCF_M (1 << I2C_ICR_ADDRCF_S)
|
||||
#define I2C_ICR_NACKCF_S 4
|
||||
#define I2C_ICR_NACKCF_M (1 << I2C_ICR_NACKCF_S)
|
||||
#define I2C_ICR_STOPCF_S 5
|
||||
#define I2C_ICR_STOPCF_M (1 << I2C_ICR_STOPCF_S)
|
||||
//
|
||||
#define I2C_ICR_BERRCF_S 8
|
||||
#define I2C_ICR_BERRCF_M (1 << I2C_ICR_BERRCF_S)
|
||||
#define I2C_ICR_ARLOCF_S 9
|
||||
#define I2C_ICR_ARLOCF_M (1 << I2C_ICR_ARLOCF_S)
|
||||
#define I2C_ICR_OVRCF_S 10
|
||||
#define I2C_ICR_OVRCF_M (1 << I2C_ICR_OVRCF_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CR1;
|
||||
volatile uint32_t CR2;
|
||||
volatile uint32_t OAR1;
|
||||
volatile uint32_t OAR2;
|
||||
volatile uint32_t TIMINGR;
|
||||
volatile uint32_t reserved0;
|
||||
volatile uint32_t ISR;
|
||||
volatile uint32_t ICR;
|
||||
volatile uint32_t reserved1;
|
||||
volatile uint32_t RXDR;
|
||||
volatile uint32_t TXDR;
|
||||
} I2C_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // I2C_H_INCLUDED
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
#ifndef OTP_H_INCLUDED
|
||||
#define OTP_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------
|
||||
// OTP register fields
|
||||
//--------------------------
|
||||
|
||||
|
||||
#define OTP_APBNWS_S 0
|
||||
#define OTP_BSY_S 0
|
||||
#define OTP_N_RA_S 8
|
||||
#define OTP_N_RSU_S 0
|
||||
#define OTP_N_RH_S 16
|
||||
#define OTP_SEL_UPP_READ 24
|
||||
#define OTP_SEL_READ_CUR 27
|
||||
|
||||
|
||||
/* Регистр управления OTPCON */
|
||||
#define OTP_OTPCON_APBNWS_S 0
|
||||
#define OTP_OTPCON_APBNWS_M (0b1 << OTP_OTPCON_APBNWS_S)
|
||||
#define OTP_OTPCON_MAN_WE_I_S 1
|
||||
#define OTP_OTPCON_MAN_WE_I_M (0b1 << OTP_OTPCON_MAN_WE_I_S)
|
||||
#define OTP_OTPCON_MAN_RE_I_S 2
|
||||
#define OTP_OTPCON_MAN_RE_I_M (0b1 << OTP_OTPCON_MAN_RE_I_S)
|
||||
#define OTP_OTPCON_MME_S 3
|
||||
#define OTP_OTPCON_MME_M (0b1 << OTP_OTPCON_MME_S)
|
||||
|
||||
/* Регистр статуса OTPSTA */
|
||||
#define OTP_OTPSTA_BSY_S 0
|
||||
#define OTP_OTPSTA_BSY_M (0b1 << OTP_OTPSTA_BSY_S)
|
||||
|
||||
/* Регистр бит дешифратора OTPDEC */
|
||||
#define OTP_OTPDEC_DECO_S 0
|
||||
#define OTP_OTPDEC_DECO_M (0x3FF << OTP_OTPDEC_DECO_S)
|
||||
|
||||
/* Регистр управления временными параметрами OTPADJ */
|
||||
#define OTP_OTPADJ_N_RSU_S 0
|
||||
#define OTP_OTPADJ_N_RSU_M (0b111 << OTP_OTPADJ_N_RSU_S)
|
||||
#define OTP_OTPADJ_N_RA_S 8
|
||||
#define OTP_OTPADJ_N_RA_M (0b111 << OTP_OTPADJ_N_RA_S)
|
||||
#define OTP_OTPADJ_N_RH_S 16
|
||||
#define OTP_OTPADJ_N_RH_M (0b111 << OTP_OTPADJ_N_RH_S)
|
||||
#define OTP_OTPADJ_SEL_UPP_READ_I_S 24
|
||||
#define OTP_OTPADJ_SEL_UPP_READ_I_M (0b111 << OTP_OTPADJ_SEL_UPP_READ_I_S)
|
||||
#define OTP_OTPADJ_SEL_UPP_READ_I_2_0V_M (0b000 << OTP_OTPADJ_SEL_UPP_READ_I_S)
|
||||
#define OTP_OTPADJ_SEL_UPP_READ_I_2_5V_M (0b001 << OTP_OTPADJ_SEL_UPP_READ_I_S)
|
||||
#define OTP_OTPADJ_SEL_UPP_READ_I_3_0V_M (0b011 << OTP_OTPADJ_SEL_UPP_READ_I_S)
|
||||
#define OTP_OTPADJ_SEL_UPP_READ_I_VDD18_M (0b010 << OTP_OTPADJ_SEL_UPP_READ_I_S)
|
||||
#define OTP_OTPADJ_SEL_UPP_READ_I_VDD5_M (0b110 << OTP_OTPADJ_SEL_UPP_READ_I_S)
|
||||
#define OTP_OTPADJ_SEL_READ_CUR_I_S 27
|
||||
#define OTP_OTPADJ_SEL_READ_CUR_I_M (0b1 << OTP_OTPADJ_SEL_READ_CUR_I_S)
|
||||
#define OTP_OTPADJ_POWER_OFF_I_S 28
|
||||
#define OTP_OTPADJ_POWER_OFF_I_M (0b1 << OTP_OTPADJ_POWER_OFF_I_S)
|
||||
|
||||
/* Регистр подстройки длительности процедуры записи 1 OTPWT1 */
|
||||
#define OTP_OTPWT1_N_SU_S 0
|
||||
#define OTP_OTPWT1_N_SU_M (0b111 << OTP_OTPWT1_N_SU_S)
|
||||
#define OTP_OTPWT1_N_H_S 8
|
||||
#define OTP_OTPWT1_N_H_M (0b111 << OTP_OTPWT1_N_H_S)
|
||||
|
||||
/* Регистр подстройки длительности процедуры записи 2 OTPWT2 */
|
||||
#define OTP_OTPWT2_N_W_S 0
|
||||
#define OTP_OTPWT2_N_W_M (0xFFFFFF << OTP_OTPWT2_N_W_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
//--------------------------
|
||||
// OTP registers
|
||||
//--------------------------
|
||||
|
||||
volatile uint32_t OTPDAT;
|
||||
volatile uint32_t OTPA;
|
||||
volatile uint32_t OTPCON;
|
||||
volatile uint32_t OTPSTA;
|
||||
volatile uint32_t OTPDEC;
|
||||
volatile uint32_t OTPADJ;
|
||||
volatile uint32_t OTPWT1;
|
||||
volatile uint32_t OTPWT2;
|
||||
|
||||
|
||||
} OTP_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif // OTP_H_INCLUDED
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
#ifndef PAD_CONFIG_H_INCLUDED
|
||||
#define PAD_CONFIG_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PAD_CONFIG_PIN_M(pin) (0b11 << ((pin) << 1))
|
||||
#define PAD_CONFIG_PIN(pin, value) ((value) << ((pin) << 1))
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t PORT_0_CFG;
|
||||
volatile uint32_t PORT_0_DS;
|
||||
volatile uint32_t PORT_0_PUPD;
|
||||
|
||||
volatile uint32_t PORT_1_CFG;
|
||||
volatile uint32_t PORT_1_DS;
|
||||
volatile uint32_t PORT_1_PUPD;
|
||||
|
||||
volatile uint32_t PORT_2_CFG;
|
||||
volatile uint32_t PORT_2_DS;
|
||||
volatile uint32_t PORT_2_PUPD;
|
||||
} PAD_CONFIG_TypeDef;
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif // PAD_CONFIG_H_INCLUDED
|
||||
@@ -0,0 +1,123 @@
|
||||
#ifndef PM_H_INCLUDED
|
||||
#define PM_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PM_DIV_AHB_OFFSET 0x00
|
||||
#define PM_DIV_APB_M_OFFSET 0x04
|
||||
#define PM_DIV_APB_P_OFFSET 0x08
|
||||
#define PM_CLK_AHB_SET_OFFSET 0x0C
|
||||
#define PM_CLK_AHB_CLEAR_OFFSET 0x10
|
||||
#define PM_CLK_APB_M_SET_OFFSET 0x14
|
||||
#define PM_CLK_APB_M_CLEAR_OFFSET 0x18
|
||||
#define PM_CLK_APB_P_SET_OFFSET 0x1C
|
||||
#define PM_CLK_APB_P_CLEAR_OFFSET 0x20
|
||||
#define PM_AHB_CLK_MUX_OFFSET 0x24
|
||||
#define PM_WDT_CLK_MUX_OFFSET 0x28
|
||||
#define PM_CPU_RTC_CLK_MUX_OFFSET 0x2C
|
||||
#define PM_TIMER_CFG_OFFSET 0x30
|
||||
#define PM_FREQ_MASK_OFFSET 0x34
|
||||
#define PM_FREQ_STATUS_OFFSET 0x38
|
||||
#define PM_SLEEP_MODE_OFFSET 0x3C
|
||||
|
||||
|
||||
#define PM_AHB_CLK_MUX_S 0
|
||||
#define PM_AHB_CLK_MUX_M (0x3 << PM_AHB_CLK_MUX_S)
|
||||
#define PM_AHB_CLK_MUX_OSC32M_M (0x0 << PM_AHB_CLK_MUX_S)
|
||||
#define PM_AHB_CLK_MUX_HSI32M_M (0x1 << PM_AHB_CLK_MUX_S)
|
||||
#define PM_AHB_CLK_MUX_OSC32K_M (0x2 << PM_AHB_CLK_MUX_S)
|
||||
#define PM_AHB_CLK_MUX_LSI32K_M (0x3 << PM_AHB_CLK_MUX_S)
|
||||
#define PM_AHB_FORCE_MUX_S 2
|
||||
#define PM_AHB_FORCE_MUX_M (1 << PM_AHB_FORCE_MUX_S)
|
||||
#define PM_AHB_FORCE_MUX_FIXED (1 << PM_AHB_FORCE_MUX_S)
|
||||
#define PM_AHB_FORCE_MUX_UNFIXED (0 << PM_AHB_FORCE_MUX_S)
|
||||
|
||||
#define PM_WDT_CLK_MUX_S 0
|
||||
#define PM_WDT_CLK_MUX_M (3 << PM_WDT_CLK_MUX_S)
|
||||
#define PM_WDT_CLK_MUX_OSC32M_M (0 << PM_WDT_CLK_MUX_S)
|
||||
#define PM_WDT_CLK_MUX_HSI32M_M (1 << PM_WDT_CLK_MUX_S)
|
||||
#define PM_WDT_CLK_MUX_OSC32K_M (2 << PM_WDT_CLK_MUX_S)
|
||||
#define PM_WDT_CLK_MUX_LSI32K_M (3 << PM_WDT_CLK_MUX_S)
|
||||
|
||||
#define PM_CPU_RTC_CLK_MUX_S 0
|
||||
#define PM_CPU_RTC_CLK_MUX_M (1 << PM_CPU_RTC_CLK_MUX_S)
|
||||
#define PM_CPU_RTC_CLK_MUX_OSC32K_M (0 << PM_CPU_RTC_CLK_MUX_S)
|
||||
#define PM_CPU_RTC_CLK_MUX_LSI32K_M (1 << PM_CPU_RTC_CLK_MUX_S)
|
||||
|
||||
#define PM_TIMER_CFG_MUX_TIMER32_0_S 0
|
||||
#define PM_TIMER_CFG_MUX_TIMER32_1_S 3
|
||||
#define PM_TIMER_CFG_MUX_TIMER32_2_S 6
|
||||
#define PM_TIMER_CFG_MUX_TIMER32_TIM1_SYS_CLK_M(timer_index) (0b00 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER32_TIM1_HCLK_M(timer_index) (0b01 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER32_TIM2_OSC32K_M(timer_index) (0b01 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER32_TIM2_LSI32K_M(timer_index) (0b10 << (timer_index))
|
||||
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_0_S 9
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_1_S 12
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_2_S 15
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_SYS_CLK_M(timer_index) (0x0 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_HCLK_M(timer_index) (0x1 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_OSC32M_M(timer_index) (0x2 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_HSI32M_M(timer_index) (0x3 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_OSC32K_M(timer_index) (0x4 << (timer_index))
|
||||
#define PM_TIMER_CFG_MUX_TIMER16_LSI32K_M(timer_index) (0x5 << (timer_index))
|
||||
|
||||
#define PM_TIMER_CFG_MUX_TIMER_M(timer_index) (0x7 << (timer_index))
|
||||
|
||||
#define PM_FREQ_MASK_FORCE_DIV_S 4
|
||||
#define PM_FREQ_MASK_FORCE_DIV_M (1 << PM_FREQ_MASK_FORCE_DIV_S)
|
||||
#define PM_FREQ_MASK_OSC32M_S 3
|
||||
#define PM_FREQ_MASK_OSC32M_M (1 << PM_FREQ_MASK_OSC32M_S)
|
||||
#define PM_FREQ_MASK_HSI32M_S 2
|
||||
#define PM_FREQ_MASK_HSI32M_M (1 << PM_FREQ_MASK_HSI32M_S)
|
||||
#define PM_FREQ_MASK_OSC32K_S 1
|
||||
#define PM_FREQ_MASK_OSC32K_M (1 << PM_FREQ_MASK_OSC32K_S)
|
||||
#define PM_FREQ_MASK_LSI32K_S 0
|
||||
#define PM_FREQ_MASK_LSI32K_M (1 << PM_FREQ_MASK_LSI32K_S)
|
||||
|
||||
#define PM_FREQ_STATUS_OSC32M_S 3
|
||||
#define PM_FREQ_STATUS_OSC32M_M (1 << PM_FREQ_STATUS_OSC32M_S)
|
||||
#define PM_FREQ_STATUS_HSI32M_S 2
|
||||
#define PM_FREQ_STATUS_HSI32M_M (1 << PM_FREQ_STATUS_HSI32M_S)
|
||||
#define PM_FREQ_STATUS_OSC32K_S 1
|
||||
#define PM_FREQ_STATUS_OSC32K_M (1 << PM_FREQ_STATUS_OSC32K_S)
|
||||
#define PM_FREQ_STATUS_LSI32K_S 0
|
||||
#define PM_FREQ_STATUS_LSI32K_M (1 << PM_FREQ_STATUS_LSI32K_S)
|
||||
|
||||
#define PM_SLEEP_MODE_S 0
|
||||
#define PM_SLEEP_MODE_M (1 << PM_SLEEP_MODE_S)
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
volatile uint32_t DIV_AHB;
|
||||
volatile uint32_t DIV_APB_M;
|
||||
volatile uint32_t DIV_APB_P;
|
||||
volatile uint32_t CLK_AHB_SET;
|
||||
volatile uint32_t CLK_AHB_CLEAR;
|
||||
volatile uint32_t CLK_APB_M_SET;
|
||||
volatile uint32_t CLK_APB_M_CLEAR;
|
||||
volatile uint32_t CLK_APB_P_SET;
|
||||
volatile uint32_t CLK_APB_P_CLEAR;
|
||||
volatile uint32_t AHB_CLK_MUX;
|
||||
volatile uint32_t WDT_CLK_MUX;
|
||||
volatile uint32_t CPU_RTC_CLK_MUX;
|
||||
volatile uint32_t TIMER_CFG;
|
||||
volatile uint32_t FREQ_MASK;
|
||||
volatile uint32_t FREQ_STATUS;
|
||||
volatile uint32_t SLEEP_MODE;
|
||||
|
||||
} PM_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
#ifndef PVD_CONTROL_H_INCLUDED
|
||||
#define PVD_CONTROL_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PVD_DPF_VALUE_S 0
|
||||
#define PVD_DPF_VALUE_M (0xFFFF << PVD_DPF_VALUE_S)
|
||||
|
||||
#define PVD_CONFIG_PD_S 0
|
||||
#define PVD_CONFIG_PD_M (1 << PVD_CONFIG_PD_S)
|
||||
#define PVD_CONFIG_NRESETU_S 1
|
||||
#define PVD_CONFIG_NRESETU_M (1 << PVD_CONFIG_NRESETU_S)
|
||||
#define PVD_CONFIG_NRESETO_S 2
|
||||
#define PVD_CONFIG_NRESETO_M (1 << PVD_CONFIG_NRESETO_S)
|
||||
#define PVD_CONFIG_TESTMODE_S 3
|
||||
#define PVD_CONFIG_TESTMODE_M (1 << PVD_CONFIG_TESTMODE_S)
|
||||
#define PVD_CONFIG_UNDER_THRESH_S 4
|
||||
#define PVD_CONFIG_UNDER_THRESH_M (0b1111 << PVD_CONFIG_UNDER_THRESH_S)
|
||||
#define PVD_CONFIG_OVER_THRESH_S 8
|
||||
#define PVD_CONFIG_OVER_THRESH_M (0b1111 << PVD_CONFIG_OVER_THRESH_S)
|
||||
#define PVD_CONFIG_EN_VREFCLB_S 12
|
||||
#define PVD_CONFIG_EN_VREFCLB_M (1 << PVD_CONFIG_EN_VREFCLB_S)
|
||||
|
||||
#define PVD_STATUS_UNDER_VALUE_S 0
|
||||
#define PVD_STATUS_UNDER_VALUE_M (1 << PVD_STATUS_UNDER_VALUE_S)
|
||||
#define PVD_STATUS_OVER_VALUE_S 1
|
||||
#define PVD_STATUS_OVER_VALUE_M (1 << PVD_STATUS_OVER_VALUE_S)
|
||||
#define PVD_STATUS_UNDER_FLAG_S 2
|
||||
#define PVD_STATUS_UNDER_FLAG_M (1 << PVD_STATUS_UNDER_FLAG_S)
|
||||
#define PVD_STATUS_OVER_FLAG_S 3
|
||||
#define PVD_STATUS_OVER_FLAG_S (1 << PVD_STATUS_OVER_FLAG_S)
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t DPF_VALUE;
|
||||
volatile uint32_t CONFIG;
|
||||
volatile uint32_t STATUS;
|
||||
} PVD_CONTROL_TypeDef;
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // PVD_CONTROL_H_INCLUDED
|
||||
|
||||
@@ -0,0 +1,119 @@
|
||||
#ifndef RTC_H_INCLUDED
|
||||
#define RTC_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RTC_TIME_OFFSET 0x00
|
||||
#define RTC_DATE_OFFSET 0x04
|
||||
#define RTC_TALRM_OFFSET 0x08
|
||||
#define RTC_DALRM_OFFSET 0x0C
|
||||
#define RTC_CTRL_OFFSET 0x10
|
||||
#define RTC_BACKUP_REG_OFFSET 0x20
|
||||
|
||||
|
||||
|
||||
#define RTC_CTRL_EN_S 31
|
||||
#define RTC_CTRL_EN_M (1 << RTC_CTRL_EN_S)
|
||||
#define RTC_CTRL_ALRM_S 30
|
||||
#define RTC_CTRL_ALRM_M (1 << RTC_CTRL_ALRM_S)
|
||||
#define RTC_CTRL_INTE_S 29
|
||||
#define RTC_CTRL_INTE_M (1 << RTC_CTRL_INTE_S)
|
||||
#define RTC_CTRL_FLAG_S 28
|
||||
#define RTC_CTRL_FLAG_M (1 << RTC_CTRL_FLAG_S)
|
||||
#define RTC_CTRL_RESET_STROBE_S 27
|
||||
#define RTC_CTRL_RESET_STROBE_M (1 << RTC_CTRL_RESET_STROBE_S)
|
||||
|
||||
|
||||
#define RTC_TALRM_CDOW_S 31
|
||||
#define RTC_TALRM_CDOW_M (1 << RTC_TALRM_CDOW_S)
|
||||
#define RTC_TALRM_CH_S 30
|
||||
#define RTC_TALRM_CH_M (1 << RTC_TALRM_CH_S)
|
||||
#define RTC_TALRM_CM_S 29
|
||||
#define RTC_TALRM_CM_M (1 << RTC_TALRM_CM_S)
|
||||
#define RTC_TALRM_CS_S 28
|
||||
#define RTC_TALRM_CS_M (1 << RTC_TALRM_CS_S)
|
||||
#define RTC_TALRM_CTOS_S 27
|
||||
#define RTC_TALRM_CTOS_M (1 << RTC_TALRM_CTOS_S)
|
||||
|
||||
#define RTC_DALRM_CC_S 30
|
||||
#define RTC_DALRM_CC_M (1 << RTC_DALRM_CC_S)
|
||||
#define RTC_DALRM_CY_S 29
|
||||
#define RTC_DALRM_CY_M (1 << RTC_DALRM_CY_S)
|
||||
#define RTC_DALRM_CM_S 28
|
||||
#define RTC_DALRM_CM_M (1 << RTC_DALRM_CM_S)
|
||||
#define RTC_DALRM_CD_S 27
|
||||
#define RTC_DALRM_CD_M (1 << RTC_DALRM_CD_S)
|
||||
|
||||
#define RTC_TIME_DOW_S 24
|
||||
#define RTC_TIME_DOW_M (0x7 << RTC_TIME_DOW_S)
|
||||
#define RTC_TIME_TH_S 22
|
||||
#define RTC_TIME_TH_M (0x3 << RTC_TIME_TH_S)
|
||||
#define RTC_TIME_H_S 18
|
||||
#define RTC_TIME_H_M (0xF << RTC_TIME_H_S)
|
||||
#define RTC_TIME_TM_S 15
|
||||
#define RTC_TIME_TM_M (0x7 << RTC_TIME_TM_S)
|
||||
#define RTC_TIME_M_S 11
|
||||
#define RTC_TIME_M_M (0xF << RTC_TIME_M_S)
|
||||
#define RTC_TIME_TS_S 8
|
||||
#define RTC_TIME_TS_M (0x7 << RTC_TIME_TS_S)
|
||||
#define RTC_TIME_S_S 4
|
||||
#define RTC_TIME_S_M (0xF << RTC_TIME_S_S)
|
||||
#define RTC_TIME_TOS_S 0
|
||||
#define RTC_TIME_TOS_M (0xF << RTC_TIME_TOS_S)
|
||||
|
||||
#define RTC_DATE_TC_S 23
|
||||
#define RTC_DATE_TC_M (0xF << RTC_DATE_TC_S)
|
||||
#define RTC_DATE_C_S 19
|
||||
#define RTC_DATE_C_M (0xF << RTC_DATE_C_S)
|
||||
#define RTC_DATE_TY_S 15
|
||||
#define RTC_DATE_TY_M (0xF << RTC_DATE_TY_S)
|
||||
#define RTC_DATE_Y_S 11
|
||||
#define RTC_DATE_Y_M (0xF << RTC_DATE_Y_S)
|
||||
#define RTC_DATE_TM_S 10
|
||||
#define RTC_DATE_TM_M (0x1 << RTC_DATE_TM_S)
|
||||
#define RTC_DATE_M_S 6
|
||||
#define RTC_DATE_M_M (0xF << RTC_DATE_M_S)
|
||||
#define RTC_DATE_TD_S 4
|
||||
#define RTC_DATE_TD_M (0x3 << RTC_DATE_TD_S)
|
||||
#define RTC_DATE_D_S 0
|
||||
#define RTC_DATE_D_M (0xF << RTC_DATE_D_S)
|
||||
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
typedef struct
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
struct {
|
||||
volatile uint32_t TOS:4;
|
||||
volatile uint32_t S:4;
|
||||
volatile uint32_t TS:3;
|
||||
volatile uint32_t M:4;
|
||||
volatile uint32_t TM:3;
|
||||
volatile uint32_t H:4;
|
||||
volatile uint32_t TH:2;
|
||||
volatile uint32_t DOW:3;
|
||||
};
|
||||
uint32_t TIME;
|
||||
};
|
||||
|
||||
volatile uint32_t DATE;
|
||||
volatile uint32_t TALRM;
|
||||
volatile uint32_t DALRM;
|
||||
volatile uint32_t CTRL;
|
||||
volatile uint32_t _space[3];
|
||||
volatile uint32_t REG[16];
|
||||
} RTC_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
#ifndef SCR1_TIMER_H_INCLUDED
|
||||
#define SCR1_TIMER_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SCR1_TIMER_CTRL_ENABLE_S 0
|
||||
#define SCR1_TIMER_CTRL_ENABLE_M (1 << SCR1_TIMER_CTRL_ENABLE_S)
|
||||
|
||||
#define SCR1_TIMER_CTRL_CLKSRC_S 1
|
||||
#define SCR1_TIMER_CTRL_CLKSRC_M (1 << SCR1_TIMER_CTRL_CLKSRC_S)
|
||||
#define SCR1_TIMER_CTRL_CLKSRC_INTERNAL_M (0 << SCR1_TIMER_CTRL_CLKSRC_S)
|
||||
#define SCR1_TIMER_CTRL_CLKSRC_RTC_M (1 << SCR1_TIMER_CTRL_CLKSRC_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t TIMER_CTRL;
|
||||
volatile uint32_t TIMER_DIV;
|
||||
volatile uint32_t MTIME;
|
||||
volatile uint32_t MTIMEH;
|
||||
volatile uint32_t MTIMECMP;
|
||||
volatile uint32_t MTIMECMPH;
|
||||
} SCR1_TIMER_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SCR1_TIMER_H_INCLUDED
|
||||
@@ -0,0 +1,123 @@
|
||||
#ifndef SPI_H_INCLUDED
|
||||
#define SPI_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SPI_CONFIG 0X00
|
||||
#define SPI_STATUS 0X04
|
||||
#define SPI_IEN 0X08
|
||||
#define SPI_IDIS 0X0C
|
||||
#define SPI_IMASK 0X10
|
||||
#define SPI_ENABLE 0X14
|
||||
#define SPI_DELAY 0X18
|
||||
#define SPI_TXD 0X1C
|
||||
#define SPI_RXD 0X20
|
||||
#define SPI_SIC 0X24
|
||||
#define SPI_THRESHOLD 0X28
|
||||
#define SPI_MODULE_ID 0XFC
|
||||
|
||||
|
||||
#define SPI_CONFIG_MANUAL_CS_S 14
|
||||
#define SPI_CONFIG_MANUAL_CS_M (1 << SPI_CONFIG_MANUAL_CS_S)
|
||||
//
|
||||
#define SPI_CONFIG_CS_S 10
|
||||
#define SPI_CONFIG_CS_M (0XF << SPI_CONFIG_CS_S)
|
||||
#define SPI_CONFIG_CS_0_M (0XE << SPI_CONFIG_CS_S)
|
||||
#define SPI_CONFIG_CS_1_M (0XD << SPI_CONFIG_CS_S)
|
||||
#define SPI_CONFIG_CS_2_M (0XB << SPI_CONFIG_CS_S)
|
||||
#define SPI_CONFIG_CS_3_M (0X7 << SPI_CONFIG_CS_S)
|
||||
#define SPI_CONFIG_CS_NONE_M (0XF << SPI_CONFIG_CS_S)
|
||||
//
|
||||
#define SPI_CONFIG_PERI_SEL_S 9
|
||||
#define SPI_CONFIG_PERI_SEL_M (1 << SPI_CONFIG_PERI_SEL_S)
|
||||
#define SPI_CONFIG_REF_CLK_S 8
|
||||
#define SPI_CONFIG_REF_CLK_M (1 << SPI_CONFIG_REF_CLK_S)
|
||||
//
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_S 3
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_M (0X7 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_2_M (0X0 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_4_M (0X1 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_8_M (0X2 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_16_M (0X3 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_32_M (0X4 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_64_M (0X5 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_128_M (0X6 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
#define SPI_CONFIG_BAUD_RATE_DIV_256_M (0X7 << SPI_CONFIG_BAUD_RATE_DIV_S)
|
||||
//
|
||||
#define SPI_MAXIMUM_BAUD_RATE_DIV 256
|
||||
//
|
||||
#define SPI_CONFIG_CLK_PH_S 2
|
||||
#define SPI_CONFIG_CLK_PH_M (1 << SPI_CONFIG_CLK_PH_S)
|
||||
#define SPI_CONFIG_CLK_POL_S 1
|
||||
#define SPI_CONFIG_CLK_POL_M (1 << SPI_CONFIG_CLK_POL_S)
|
||||
#define SPI_CONFIG_MODE_SEL_S 0
|
||||
#define SPI_CONFIG_MODE_SEL_M (1 << SPI_CONFIG_MODE_SEL_S)
|
||||
#define SPI_CONFIG_MASTER_M (1 << SPI_CONFIG_MODE_SEL_S)
|
||||
#define SPI_CONFIG_SLAVE_M (0 << SPI_CONFIG_MODE_SEL_S)
|
||||
|
||||
|
||||
#define SPI_ENABLE_CLEAR_RX_FIFO_S 3
|
||||
#define SPI_ENABLE_CLEAR_RX_FIFO_M (1 << SPI_ENABLE_CLEAR_RX_FIFO_S)
|
||||
#define SPI_ENABLE_CLEAR_TX_FIFO_S 2
|
||||
#define SPI_ENABLE_CLEAR_TX_FIFO_M (1 << SPI_ENABLE_CLEAR_TX_FIFO_S)
|
||||
#define SPI_ENABLE_S 0
|
||||
#define SPI_ENABLE_M (1 << SPI_ENABLE_S)
|
||||
|
||||
|
||||
#define SPI_DELAY_BTWN_S 16
|
||||
#define SPI_DELAY_BTWN_M (0XFF << SPI_DELAY_BTWN_S)
|
||||
#define SPI_DELAY_BTWN(V) (((V) << SPI_DELAY_BTWN_S) & SPI_DELAY_BTWN_M)
|
||||
#define SPI_DELAY_AFTER_S 8
|
||||
#define SPI_DELAY_AFTER_M (0XFF << SPI_DELAY_AFTER_S)
|
||||
#define SPI_DELAY_AFTER(V) (((V) << SPI_DELAY_AFTER_S) & SPI_DELAY_AFTER_M)
|
||||
#define SPI_DELAY_INIT_S 0
|
||||
#define SPI_DELAY_INIT_M (0XFF << SPI_DELAY_INIT_S)
|
||||
#define SPI_DELAY_INIT(V) (((V) << SPI_DELAY_INIT_S) & SPI_DELAY_INIT_M)
|
||||
|
||||
|
||||
#define SPI_INT_STATUS_SPI_ACTIVE_S 15
|
||||
#define SPI_INT_STATUS_SPI_ACTIVE_M (1 << SPI_INT_STATUS_SPI_ACTIVE_S)
|
||||
#define SPI_INT_STATUS_TX_FIFO_UNDERFLOW_S 6
|
||||
#define SPI_INT_STATUS_TX_FIFO_UNDERFLOW_M (1 << SPI_INT_STATUS_TX_FIFO_UNDERFLOW_S)
|
||||
#define SPI_INT_STATUS_RX_OVERFLOW_S 0
|
||||
#define SPI_INT_STATUS_RX_OVERFLOW_M (1 << SPI_INT_STATUS_RX_OVERFLOW_S)
|
||||
#define SPI_INT_STATUS_MODE_FAIL_S 1
|
||||
#define SPI_INT_STATUS_MODE_FAIL_M (1 << SPI_INT_STATUS_MODE_FAIL_S)
|
||||
#define SPI_INT_STATUS_TX_FIFO_NOT_FULL_S 2
|
||||
#define SPI_INT_STATUS_TX_FIFO_NOT_FULL_M (1 << SPI_INT_STATUS_TX_FIFO_NOT_FULL_S)
|
||||
#define SPI_INT_STATUS_TX_FIFO_FULL_S 3
|
||||
#define SPI_INT_STATUS_TX_FIFO_FULL_M (1 << SPI_INT_STATUS_TX_FIFO_FULL_S)
|
||||
#define SPI_INT_STATUS_RX_FIFO_NOT_EMPTY_S 4
|
||||
#define SPI_INT_STATUS_RX_FIFO_NOT_EMPTY_M (1 << SPI_INT_STATUS_RX_FIFO_NOT_EMPTY_S)
|
||||
#define SPI_INT_STATUS_RX_FIFO_FULL_S 5
|
||||
#define SPI_INT_STATUS_RX_FIFO_FULL_M (1 << SPI_INT_STATUS_RX_FIFO_FULL_S)
|
||||
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CONFIG; /* Offset: 0x000 (R/W) */
|
||||
volatile uint32_t INT_STATUS; /* Offset: 0x004 (R/RC) */
|
||||
volatile uint32_t INT_ENABLE; /* Offset: 0x008 (WO) */
|
||||
volatile uint32_t INT_DISABLE; /* Offset: 0x00C (WO) */
|
||||
volatile uint32_t INT_MASK; /* Offset: 0x010 (R) */
|
||||
volatile uint32_t ENABLE; /* Offset: 0x014 (R/W) */
|
||||
volatile uint32_t DELAY; /* Offset: 0x018 (R/W) */
|
||||
volatile uint32_t TXDATA; /* Offset: 0x01C (WO) */
|
||||
volatile uint32_t RXDATA; /* Offset: 0x020 (RO) */
|
||||
volatile uint32_t SIC; /* Offset: 0x024 (R/W) Slave_Idle_Count */
|
||||
volatile uint32_t TX_THR; /* Offset: 0x028 (R/W) TX threshold */
|
||||
volatile uint32_t reserved[0X34]; /* Empty array to fill the space*/
|
||||
volatile uint32_t ID; /* Offset: 0x0FC (RO) Module ID 0x01090100 */
|
||||
}SPI_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SPI_H_INCLUDED
|
||||
@@ -0,0 +1,137 @@
|
||||
#ifndef SPIFI_H_INCLUDED
|
||||
#define SPIFI_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//CTRL
|
||||
#define SPIFI_CONFIG_CTRL_TIMEOUT_S 0
|
||||
#define SPIFI_CONFIG_CTRL_TIMEOUT_M (0xFFFF << SPIFI_CONFIG_CTRL_TIMEOUT_S)
|
||||
#define SPIFI_CONFIG_CTRL_TIMEOUT(v) (((v) << SPIFI_CONFIG_CTRL_TIMEOUT_S) & SPIFI_CONFIG_CTRL_TIMEOUT_M)
|
||||
#define SPIFI_CONFIG_CTRL_CSHIGH_S 16
|
||||
#define SPIFI_CONFIG_CTRL_CSHIGH_M (0xF << SPIFI_CONFIG_CTRL_CSHIGH_S)
|
||||
#define SPIFI_CONFIG_CTRL_CSHIGH(v) (((v) << SPIFI_CONFIG_CTRL_CSHIGH_S) & SPIFI_CONFIG_CTRL_CSHIGH_M)
|
||||
#define SPIFI_CONFIG_CTRL_CACHE_EN_S 20
|
||||
#define SPIFI_CONFIG_CTRL_CACHE_EN_M (0x1 << SPIFI_CONFIG_CTRL_CACHE_EN_S)
|
||||
#define SPIFI_CONFIG_CTRL_D_CACHE_DIS_S 21
|
||||
#define SPIFI_CONFIG_CTRL_D_CACHE_DIS_M (0x1 << SPIFI_CONFIG_CTRL_D_CACHE_DIS_S)
|
||||
#define SPIFI_CONFIG_CTRL_INTEN_S 22
|
||||
#define SPIFI_CONFIG_CTRL_INTEN_M (0x1 << SPIFI_CONFIG_CTRL_INTEN_S)
|
||||
#define SPIFI_CONFIG_CTRL_MODE3_S 23
|
||||
#define SPIFI_CONFIG_CTRL_MODE3_M (0x1 << SPIFI_CONFIG_CTRL_MODE3_S)
|
||||
#define SPIFI_CONFIG_CTRL_SCK_DIV_S 24
|
||||
#define SPIFI_CONFIG_CTRL_SCK_DIV_M (0x7 << SPIFI_CONFIG_CTRL_SCK_DIV_S)
|
||||
#define SPIFI_CONFIG_CTRL_SCK_DIV(v) (((v) << SPIFI_CONFIG_CTRL_SCK_DIV_S) & SPIFI_CONFIG_CTRL_SCK_DIV_M)
|
||||
#define SPIFI_CONFIG_CTRL_PREFETCH_DIS_S 27
|
||||
#define SPIFI_CONFIG_CTRL_PREFETCH_DIS_M (0x1 << SPIFI_CONFIG_CTRL_PREFETCH_DIS_S)
|
||||
#define SPIFI_CONFIG_CTRL_DUAL_S 28
|
||||
#define SPIFI_CONFIG_CTRL_DUAL_M (0x1 << SPIFI_CONFIG_CTRL_DUAL_S)
|
||||
#define SPIFI_CONFIG_CTRL_RFCLK_S 29
|
||||
#define SPIFI_CONFIG_CTRL_RFCLK_M (0x1 << SPIFI_CONFIG_CTRL_RFCLK_S)
|
||||
#define SPIFI_CONFIG_CTRL_FBCLK_S 30
|
||||
#define SPIFI_CONFIG_CTRL_FBCLK_M (0x1 << SPIFI_CONFIG_CTRL_FBCLK_S)
|
||||
#define SPIFI_CONFIG_CTRL_DMAEN_S 31
|
||||
#define SPIFI_CONFIG_CTRL_DMAEN_M (0x1 << SPIFI_CONFIG_CTRL_DMAEN_S)
|
||||
|
||||
//CMD
|
||||
#define SPIFI_CONFIG_CMD_DATALEN_S 0
|
||||
#define SPIFI_CONFIG_CMD_DATALEN_M (0x3FFF << SPIFI_CONFIG_CMD_DATALEN_S)
|
||||
#define SPIFI_CONFIG_CMD_DATALEN(v) (((v) << SPIFI_CONFIG_CMD_DATALEN_S) & SPIFI_CONFIG_CMD_DATALEN_M)
|
||||
#define SPIFI_CONFIG_CMD_POLL_INDEX_S 0
|
||||
#define SPIFI_CONFIG_CMD_POLL_INDEX_M (0b111 << SPIFI_CONFIG_CMD_POLL_INDEX_S)
|
||||
#define SPIFI_CONFIG_CMD_POLL_INDEX(v) (((v) << SPIFI_CONFIG_CMD_POLL_INDEX_S) & SPIFI_CONFIG_CMD_POLL_INDEX_M)
|
||||
#define SPIFI_CONFIG_CMD_POLL_REQUIRED_VALUE_S 3
|
||||
#define SPIFI_CONFIG_CMD_POLL_REQUIRED_VALUE_M (1 << SPIFI_CONFIG_CMD_POLL_REQUIRED_VALUE_S)
|
||||
#define SPIFI_CONFIG_CMD_POLL_REQUIRED_VALUE(v) (((v) << SPIFI_CONFIG_CMD_POLL_REQUIRED_VALUE_S) & SPIFI_CONFIG_CMD_POLL_REQUIRED_VALUE_M)
|
||||
#define SPIFI_CONFIG_CMD_POLL_S 14
|
||||
#define SPIFI_CONFIG_CMD_POLL_M (0x1 << SPIFI_CONFIG_CMD_POLL_S)
|
||||
#define SPIFI_CONFIG_CMD_DOUT_S 15
|
||||
#define SPIFI_CONFIG_CMD_DOUT_M (0x1 << SPIFI_CONFIG_CMD_DOUT_S)
|
||||
#define SPIFI_CONFIG_CMD_INTLEN_S 16
|
||||
#define SPIFI_CONFIG_CMD_INTLEN_M (0x7 << SPIFI_CONFIG_CMD_INTLEN_S)
|
||||
#define SPIFI_CONFIG_CMD_INTLEN(v) (((v) << SPIFI_CONFIG_CMD_INTLEN_S) & SPIFI_CONFIG_CMD_INTLEN_M)
|
||||
#define SPIFI_CONFIG_CMD_FIELDFORM_S 19
|
||||
#define SPIFI_CONFIG_CMD_FIELDFORM_M (0x3 << SPIFI_CONFIG_CMD_FIELDFORM_S)
|
||||
#define SPIFI_CONFIG_CMD_FIELDFORM(v) (((v) << SPIFI_CONFIG_CMD_FIELDFORM_S) & SPIFI_CONFIG_CMD_FIELDFORM_M)
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_S 21
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_M (0x7 << SPIFI_CONFIG_CMD_FRAMEFORM_S)
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM(v) (((v) << SPIFI_CONFIG_CMD_FRAMEFORM_S) & SPIFI_CONFIG_CMD_FRAMEFORM_M)
|
||||
#define SPIFI_CONFIG_CMD_OPCODE_S 24
|
||||
#define SPIFI_CONFIG_CMD_OPCODE_M (0xFF << SPIFI_CONFIG_CMD_OPCODE_S)
|
||||
#define SPIFI_CONFIG_CMD_OPCODE(v) (((v) << SPIFI_CONFIG_CMD_OPCODE_S) & SPIFI_CONFIG_CMD_OPCODE_M)
|
||||
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_RESERVED 0
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_NOADDR 1
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_1ADDR 2
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_2ADDR 3
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR 4
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_4ADDR 5
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_3ADDR 6
|
||||
#define SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_4ADDR 7
|
||||
|
||||
#define SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL 0
|
||||
#define SPIFI_CONFIG_CMD_FIELDFORM_DATA_PARALLEL 1
|
||||
#define SPIFI_CONFIG_CMD_FIELDFORM_OPCODE_SERIAL 2
|
||||
#define SPIFI_CONFIG_CMD_FIELDFORM_ALL_PARALLEL 3
|
||||
|
||||
//ADDR
|
||||
//IDATA
|
||||
//CLIMIT
|
||||
//DATA
|
||||
|
||||
//MCMD
|
||||
#define SPIFI_CONFIG_MCMD_POLL_S 14
|
||||
#define SPIFI_CONFIG_MCMD_POLL_M (0x1 << SPIFI_CONFIG_MCMD_POLL_S)
|
||||
#define SPIFI_CONFIG_MCMD_DOUT_S 15
|
||||
#define SPIFI_CONFIG_MCMD_DOUT_M (0x1 << SPIFI_CONFIG_MCMD_DOUT_S)
|
||||
#define SPIFI_CONFIG_MCMD_INTLEN_S 16
|
||||
#define SPIFI_CONFIG_MCMD_INTLEN_M (0x7 << SPIFI_CONFIG_MCMD_INTLEN_S)
|
||||
#define SPIFI_CONFIG_MCMD_FIELDFORM_S 19
|
||||
#define SPIFI_CONFIG_MCMD_FIELDFORM_M (0x3 << SPIFI_CONFIG_MCMD_FIELDFORM_S)
|
||||
#define SPIFI_CONFIG_MCMD_FRAMEFORM_S 21
|
||||
#define SPIFI_CONFIG_MCMD_FRAMEFORM_M (0x7 << SPIFI_CONFIG_MCMD_FRAMEFORM_S)
|
||||
#define SPIFI_CONFIG_MCMD_OPCODE_S 24
|
||||
#define SPIFI_CONFIG_MCMD_OPCODE_M (0xFF << SPIFI_CONFIG_MCMD_OPCODE_S)
|
||||
|
||||
//STATUS
|
||||
#define SPIFI_CONFIG_STAT_MCINIT_S 0
|
||||
#define SPIFI_CONFIG_STAT_MCINIT_M (0x1 << SPIFI_CONFIG_STAT_MCINIT_S)
|
||||
#define SPIFI_CONFIG_STAT_CMD_S 1
|
||||
#define SPIFI_CONFIG_STAT_CMD_M (0x1 << SPIFI_CONFIG_STAT_CMD_S)
|
||||
#define SPIFI_CONFIG_STAT_RESET_S 4
|
||||
#define SPIFI_CONFIG_STAT_RESET_M (0x1 << SPIFI_CONFIG_STAT_RESET_S)
|
||||
#define SPIFI_CONFIG_STAT_INTRQ_S 5
|
||||
#define SPIFI_CONFIG_STAT_INTRQ_M (0x1 << SPIFI_CONFIG_STAT_INTRQ_S)
|
||||
#define SPIFI_CONFIG_STAT_VERSION_S 24
|
||||
#define SPIFI_CONFIG_STAT_VERSION_M (0xFF << SPIFI_CONFIG_STAT_VERSION_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CTRL; //Offset: 0x000
|
||||
volatile uint32_t CMD; //Offset: 0x004
|
||||
volatile uint32_t ADDR; //Offset: 0x008
|
||||
volatile uint32_t IDATA; //Offset: 0x00C
|
||||
volatile uint32_t CLIMIT; //Offset: 0x010
|
||||
union
|
||||
{
|
||||
volatile uint32_t DATA; //Offset: 0x014
|
||||
volatile uint8_t DATA8;
|
||||
volatile uint16_t DATA16;
|
||||
volatile uint32_t DATA32;
|
||||
};
|
||||
|
||||
volatile uint32_t MCMD; //Offset: 0x018
|
||||
volatile uint32_t STAT; //Offset: 0x01C
|
||||
}SPIFI_CONFIG_TypeDef;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SPIFI_H_INCLUDED
|
||||
@@ -0,0 +1,178 @@
|
||||
#ifndef TIMER16_H_INCLUDED
|
||||
#define TIMER16_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define TIMER16_SYNC_CLOCKS 2
|
||||
|
||||
#define TIMER16_ISR 0x00
|
||||
#define TIMER16_ICR 0x04
|
||||
#define TIMER16_IER 0x08
|
||||
#define TIMER16_CFGR 0x0C
|
||||
#define TIMER16_CR 0x10
|
||||
#define TIMER16_CMP 0x14
|
||||
#define TIMER16_ARR 0x18
|
||||
#define TIMER16_CNT 0x1C
|
||||
|
||||
#define TIMER16_ENABLE_S 0
|
||||
#define TIMER16_ENABLE_M (1 << TIMER16_ENABLE_S)
|
||||
#define TIMER16_DISABLE_M (0 << TIMER16_ENABLE_S)
|
||||
#define TIMER16_START_SINGLE_MODE_S 1
|
||||
#define TIMER16_START_SINGLE_MODE_M (1 << TIMER16_START_SINGLE_MODE_S)
|
||||
#define TIMER16_START_CONTIN_MODE_S 2
|
||||
#define TIMER16_START_CONTIN_MODE_M (1 << TIMER16_START_CONTIN_MODE_S)
|
||||
|
||||
|
||||
#define TIMER16_PRESCALER_S 9
|
||||
#define TIMER16_PRESCALER_1_M (0x0 << TIMER16_PRESCALER_S)
|
||||
#define TIMER16_PRESCALER_2_M (0x1 << TIMER16_PRESCALER_S)
|
||||
#define TIMER16_PRESCALER_4_M (0x2 << TIMER16_PRESCALER_S)
|
||||
#define TIMER16_PRESCALER_8_M (0x3 << TIMER16_PRESCALER_S)
|
||||
#define TIMER16_PRESCALER_16_M (0x4 << TIMER16_PRESCALER_S)
|
||||
#define TIMER16_PRESCALER_32_M (0x5 << TIMER16_PRESCALER_S)
|
||||
#define TIMER16_PRESCALER_64_M (0x6 << TIMER16_PRESCALER_S)
|
||||
#define TIMER16_PRESCALER_128_M (0x7 << TIMER16_PRESCALER_S)
|
||||
|
||||
// Alias for CFGR.ENC bit
|
||||
#define TIMER16_ENCODER_S 24
|
||||
#define TIMER16_ENCODER_DISABLE_M (0x0 << TIMER16_ENCODER_S)
|
||||
#define TIMER16_ENCODER_ENABLE_M (0x1 << TIMER16_ENCODER_S)
|
||||
|
||||
// Маски и сдвиги флагов прерываний
|
||||
#define TIMER16_INT_CMP_MATCH_S 0
|
||||
#define TIMER16_INT_CMP_MATCH_M (0x1 << TIMER16_INT_CMP_MATCH_S)
|
||||
#define TIMER16_INT_ARR_MATCH_S 1
|
||||
#define TIMER16_INT_ARR_MATCH_M (0x1 << TIMER16_INT_ARR_MATCH_S)
|
||||
#define TIMER16_INT_EXT_TRIG_S 2
|
||||
#define TIMER16_INT_EXT_TRIG_M (0x1 << TIMER16_INT_EXT_TRIG_S)
|
||||
#define TIMER16_INT_CMP_OK_S 3
|
||||
#define TIMER16_INT_CMP_OK_M (0x1 << TIMER16_INT_CMP_OK_S)
|
||||
#define TIMER16_INT_ARR_OK_S 4
|
||||
#define TIMER16_INT_ARR_OK_M (0x1 << TIMER16_INT_ARR_OK_S)
|
||||
#define TIMER16_INT_UP_S 5
|
||||
#define TIMER16_INT_UP_M (0x1 << TIMER16_INT_UP_S)
|
||||
#define TIMER16_INT_DOWN_S 6
|
||||
#define TIMER16_INT_DOWN_M (0x1 << TIMER16_INT_DOWN_S)
|
||||
|
||||
// Регистр ISR
|
||||
#define TIMER16_ISR_CMP_MATCH_S 0
|
||||
#define TIMER16_ISR_CMP_MATCH_M (0x1 << TIMER16_ISR_CMP_MATCH_S)
|
||||
#define TIMER16_ISR_ARR_MATCH_S 1
|
||||
#define TIMER16_ISR_ARR_MATCH_M (0x1 << TIMER16_ISR_ARR_MATCH_S)
|
||||
#define TIMER16_ISR_EXT_TRIG_S 2
|
||||
#define TIMER16_ISR_EXT_TRIG_M (0x1 << TIMER16_ISR_EXT_TRIG_S)
|
||||
#define TIMER16_ISR_CMP_OK_S 3
|
||||
#define TIMER16_ISR_CMP_OK_M (0x1 << TIMER16_ISR_CMP_OK_S)
|
||||
#define TIMER16_ISR_ARR_OK_S 4
|
||||
#define TIMER16_ISR_ARR_OK_M (0x1 << TIMER16_ISR_ARR_OK_S)
|
||||
#define TIMER16_ISR_UP_S 5
|
||||
#define TIMER16_ISR_UP_M (0x1 << TIMER16_ISR_UP_S)
|
||||
#define TIMER16_ISR_DOWN_S 6
|
||||
#define TIMER16_ISR_DOWN_M (0x1 << TIMER16_ISR_DOWN_S)
|
||||
|
||||
// Регистр ICR
|
||||
#define TIMER16_ICR_DOWNCF_S 6
|
||||
#define TIMER16_ICR_DOWNCF_M (0x1 << TIMER16_ICR_DOWNCF_S)
|
||||
#define TIMER16_ICR_UPCF_S 5
|
||||
#define TIMER16_ICR_UPCF_M (0x1 << TIMER16_ICR_UPCF_S)
|
||||
#define TIMER16_ICR_ARROKCF_S 4
|
||||
#define TIMER16_ICR_ARROKCF_M (0x1 << TIMER16_ICR_ARROKCF_S)
|
||||
#define TIMER16_ICR_CMPOKCF_S 3
|
||||
#define TIMER16_ICR_CMPOKCF_M (0x1 << TIMER16_ICR_CMPOKCF_S)
|
||||
#define TIMER16_ICR_EXTTRIGCF_S 2
|
||||
#define TIMER16_ICR_EXTTRIGCF_M (0x1 << TIMER16_ICR_EXTTRIGCF_S)
|
||||
#define TIMER16_ICR_ARRMCF_S 1
|
||||
#define TIMER16_ICR_ARRMCF_M (0x1 << TIMER16_ICR_ARRMCF_S)
|
||||
#define TIMER16_ICR_CMPMCF_S 0
|
||||
#define TIMER16_ICR_CMPMCF_M (0x1 << TIMER16_ICR_CMPMCF_S)
|
||||
|
||||
// Регистр IER
|
||||
#define TIMER16_IER_DOWNIE_S 6
|
||||
#define TIMER16_IER_DOWNIE_M (0x1 << TIMER16_IER_DOWNIE_S)
|
||||
#define TIMER16_IER_UPIE_S 5
|
||||
#define TIMER16_IER_UPIE_M (0x1 << TIMER16_IER_UPIE_S)
|
||||
#define TIMER16_IER_ARROKIE_S 4
|
||||
#define TIMER16_IER_ARROKIE_M (0x1 << TIMER16_IER_ARROKIE_S)
|
||||
#define TIMER16_IER_CMPOKIE_S 3
|
||||
#define TIMER16_IER_CMPOKIE_M (0x1 << TIMER16_IER_CMPOKIE_S)
|
||||
#define TIMER16_IER_EXTTRIGIE_S 2
|
||||
#define TIMER16_IER_EXTTRIGIE_M (0x1 << TIMER16_IER_EXTTRIGIE_S)
|
||||
#define TIMER16_IER_ARRMIE_S 1
|
||||
#define TIMER16_IER_ARRMIE_M (0x1 << TIMER16_IER_ARRMIE_S)
|
||||
#define TIMER16_IER_CMPMIE_S 0
|
||||
#define TIMER16_IER_CMPMIE_M (0x1 << TIMER16_IER_CMPMIE_S)
|
||||
|
||||
// Регистр CFGR
|
||||
#define TIMER16_CFGR_ENC_S 24
|
||||
#define TIMER16_CFGR_ENC_M (1 << TIMER16_CFGR_ENC_S)
|
||||
#define TIMER16_CFGR_COUNTMODE_S 23
|
||||
#define TIMER16_CFGR_COUNTMODE_M (1 << TIMER16_CFGR_COUNTMODE_S)
|
||||
#define TIMER16_CFGR_PRELOAD_S 22
|
||||
#define TIMER16_CFGR_PRELOAD_M (1 << TIMER16_CFGR_PRELOAD_S)
|
||||
#define TIMER16_CFGR_WAVPOL_S 21
|
||||
#define TIMER16_CFGR_WAVPOL_M (1 << TIMER16_CFGR_WAVPOL_S)
|
||||
#define TIMER16_CFGR_WAVE_S 20
|
||||
#define TIMER16_CFGR_WAVE_M (1 << TIMER16_CFGR_WAVE_S)
|
||||
#define TIMER16_CFGR_TIMOUT_S 19
|
||||
#define TIMER16_CFGR_TIMOUT_M (1 << TIMER16_CFGR_TIMOUT_S)
|
||||
#define TIMER16_CFGR_TRIGEN_S 17
|
||||
#define TIMER16_CFGR_TRIGEN_M (0x3 << TIMER16_CFGR_TRIGEN_S)
|
||||
//
|
||||
#define TIMER16_CFGR_TRIGSEL_S 13
|
||||
#define TIMER16_CFGR_TRIGSEL_M (0x7 << TIMER16_CFGR_TRIGSEL_S)
|
||||
#define TIMER16_CFGR_PRESC_S 9
|
||||
#define TIMER16_CFGR_PRESC_M (0x111 << TIMER16_CFGR_PRESC_S)
|
||||
//
|
||||
#define TIMER16_CFGR_TRGFLT_S 6
|
||||
#define TIMER16_CFGR_TRGFLT_M (0x3 << TIMER16_CFGR_TRGFLT_S)
|
||||
#define TIMER16_CFGR_TRGFLT_DISABLED_M (0x0 << TIMER16_CFGR_TRGFLT_S)
|
||||
#define TIMER16_CFGR_TRGFLT_2_M (0x1 << TIMER16_CFGR_TRGFLT_S)
|
||||
#define TIMER16_CFGR_TRGFLT_4_M (0x2 << TIMER16_CFGR_TRGFLT_S)
|
||||
#define TIMER16_CFGR_TRGFLT_8_M (0x3 << TIMER16_CFGR_TRGFLT_S)
|
||||
#define TIMER16_CFGR_CKFLT_S 3
|
||||
#define TIMER16_CFGR_CKFLT_M (0x3 << TIMER16_CFGR_CKFLT_S)
|
||||
#define TIMER16_CFGR_CKFLT_DISABLED_M (0x0 << TIMER16_CFGR_CKFLT_S)
|
||||
#define TIMER16_CFGR_CKFLT_2_M (0x1 << TIMER16_CFGR_CKFLT_S)
|
||||
#define TIMER16_CFGR_CKFLT_4_M (0x2 << TIMER16_CFGR_CKFLT_S)
|
||||
#define TIMER16_CFGR_CKFLT_8_M (0x3 << TIMER16_CFGR_CKFLT_S)
|
||||
#define TIMER16_CFGR_CKPOL_S 1
|
||||
#define TIMER16_CFGR_CKPOL_M (0x3 << TIMER16_CFGR_CKPOL_S)
|
||||
#define TIMER16_CFGR_CKPOL_RISING_M (0x0 << TIMER16_CFGR_CKPOL_S)
|
||||
#define TIMER16_CFGR_CKPOL_FALLING_M (0x1 << TIMER16_CFGR_CKPOL_S)
|
||||
#define TIMER16_CFGR_CKPOL_ANY_M (0x2 << TIMER16_CFGR_CKPOL_S)
|
||||
#define TIMER16_CFGR_CKSEL_S 0
|
||||
#define TIMER16_CFGR_CKSEL_M (1 << TIMER16_CFGR_CKSEL_S)
|
||||
#define TIMER16_CFGR_CKSEL_INTERNAL_M (0x0 << TIMER16_CFGR_CKSEL_S)
|
||||
#define TIMER16_CFGR_CKSEL_EXTERNAL_M (0x1 << TIMER16_CFGR_CKSEL_S)
|
||||
|
||||
// Регистр CR
|
||||
#define TIMER16_CR_CNTSTRT_S 2
|
||||
#define TIMER16_CR_CNTSTRT_M (1 << TIMER16_CR_CNTSTRT_S)
|
||||
#define TIMER16_CR_SNGSTRT_S 1
|
||||
#define TIMER16_CR_SNGSTRT_M (1 << TIMER16_CR_SNGSTRT_S)
|
||||
#define TIMER16_CR_ENABLE_S 0
|
||||
#define TIMER16_CR_ENABLE_M (1 << TIMER16_CR_ENABLE_S)
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t ISR;
|
||||
volatile uint32_t ICR;
|
||||
volatile uint32_t IER;
|
||||
volatile uint32_t CFGR;
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t CMP;
|
||||
volatile uint32_t ARR;
|
||||
volatile uint32_t CNT;
|
||||
} TIMER16_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // TIMER16_H_INCLUDED
|
||||
@@ -0,0 +1,123 @@
|
||||
#ifndef TIMER32_H_INCLUDED
|
||||
#define TIMER32_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define TIMER32_VALUE 0x00
|
||||
#define TIMER32_TOP 0x04
|
||||
#define TIMER32_PRESCALER 0x08
|
||||
#define TIMER32_CONTROL 0x0C
|
||||
#define TIMER32_ENABLE 0x10
|
||||
|
||||
#define TIMER32_INT_MASK 0x14
|
||||
#define TIMER32_INT_CLEAR 0x18
|
||||
#define TIMER32_INT_FLAGS 0x1C
|
||||
|
||||
#define TIMER32_CH_BASE 0x80
|
||||
#define TIMER32_CH_CONTROL_OFFSET 0x00
|
||||
#define TIMER32_CH_OCR_OFFSET 0x04
|
||||
#define TIMER32_CH_ICR_OFFSET 0x08
|
||||
#define TIMER32_CH_SIZE 0x10
|
||||
|
||||
|
||||
// PRESCALER
|
||||
#define TIMER32_PRESCALER_ENABLE_S 8
|
||||
#define TIMER32_PRESCALER_ENABLE_M (1 << TIMER32_PRESCALER_ENABLE_S)
|
||||
#define TIMER32_PRESCALER_DISABLE_M (0 << TIMER32_PRESCALER_ENABLE_S)
|
||||
//
|
||||
#define TIMER32_PRESCALER_S 0
|
||||
#define TIMER32_PRESCALER_M (0xFF << TIMER32_PRESCALER_S)
|
||||
|
||||
// CONTROL
|
||||
#define TIMER32_CONTROL_CLOCK_S 2
|
||||
#define TIMER32_CONTROL_CLOCK_M (0x3 << TIMER32_CONTROL_CLOCK_S)
|
||||
#define TIMER32_CONTROL_CLOCK_PRESCALER_M (0x0 << TIMER32_CONTROL_CLOCK_S)
|
||||
#define TIMER32_CONTROL_CLOCK_TIM1_M (0x1 << TIMER32_CONTROL_CLOCK_S)
|
||||
#define TIMER32_CONTROL_CLOCK_TX_PIN_M (0x2 << TIMER32_CONTROL_CLOCK_S)
|
||||
#define TIMER32_CONTROL_CLOCK_TIM2_M (0x3 << TIMER32_CONTROL_CLOCK_S)
|
||||
//
|
||||
#define TIMER32_CONTROL_MODE_S 0
|
||||
#define TIMER32_CONTROL_MODE_M (0x3 << TIMER32_CONTROL_MODE_S)
|
||||
#define TIMER32_CONTROL_MODE_UP_M (0 << TIMER32_CONTROL_MODE_S)
|
||||
#define TIMER32_CONTROL_MODE_DOWN_M (1 << TIMER32_CONTROL_MODE_S)
|
||||
#define TIMER32_CONTROL_MODE_BIDIR_M (2 << TIMER32_CONTROL_MODE_S)
|
||||
|
||||
// ENABLE
|
||||
#define TIMER32_ENABLE_TIM_CLR_S 1
|
||||
#define TIMER32_ENABLE_TIM_CLR_M (1 << TIMER32_ENABLE_TIM_CLR_S)
|
||||
//
|
||||
#define TIMER32_ENABLE_TIM_EN_S 0
|
||||
#define TIMER32_ENABLE_TIM_EN_M (1 << TIMER32_ENABLE_TIM_EN_S)
|
||||
|
||||
// INT_MASK, INT_CLEAR, INT_FLAGS
|
||||
#define TIMER32_INT_OVERFLOW_S 0
|
||||
#define TIMER32_INT_OVERFLOW_M (1 << TIMER32_INT_OVERFLOW_S)
|
||||
#define TIMER32_INT_UNDERFLOW_S 1
|
||||
#define TIMER32_INT_UNDERFLOW_M (1 << TIMER32_INT_UNDERFLOW_S)
|
||||
#define TIMER32_INT_IC_S 2
|
||||
#define TIMER32_INT_IC_M(channelIndex) ((1 << channelIndex) << TIMER32_INT_IC_S)
|
||||
#define TIMER32_INT_OC_S 6
|
||||
#define TIMER32_INT_OC_M(channelIndex) ((1 << channelIndex) << TIMER32_INT_OC_S)
|
||||
|
||||
|
||||
//CH_CNTRL
|
||||
#define TIMER32_CH_CNTRL_NOISE_S 0
|
||||
#define TIMER32_CH_CNTRL_NOISE_M (1 << TIMER32_CH_CNTRL_NOISE_S)
|
||||
//
|
||||
#define TIMER32_CH_CNTRL_CAPTURE_EDGE_S 4
|
||||
#define TIMER32_CH_CNTRL_CAPTURE_EDGE_M (1 << TIMER32_CH_CNTRL_CAPTURE_EDGE_S)
|
||||
#define TIMER32_CH_CNTRL_CAPTURE_POS_M (0 << TIMER32_CH_CNTRL_CAPTURE_EDGE_S)
|
||||
#define TIMER32_CH_CNTRL_CAPTURE_NEG_M (1 << TIMER32_CH_CNTRL_CAPTURE_EDGE_S)
|
||||
//
|
||||
#define TIMER32_CH_CNTRL_MODE_S 5
|
||||
#define TIMER32_CH_CNTRL_MODE_M (3 << TIMER32_CH_CNTRL_MODE_S)
|
||||
#define TIMER32_CH_CNTRL_MODE_COMPARE_M (1 << TIMER32_CH_CNTRL_MODE_S)
|
||||
#define TIMER32_CH_CNTRL_MODE_CAPTURE_M (2 << TIMER32_CH_CNTRL_MODE_S)
|
||||
#define TIMER32_CH_CNTRL_MODE_PWM_M (3 << TIMER32_CH_CNTRL_MODE_S)
|
||||
//
|
||||
#define TIMER32_CH_CNTRL_ENABLE_S 7
|
||||
#define TIMER32_CH_CNTRL_ENABLE_M (1 << TIMER32_CH_CNTRL_ENABLE_S)
|
||||
#define TIMER32_CH_CNTRL_DISABLE_M (0 << TIMER32_CH_CNTRL_ENABLE_S)
|
||||
//
|
||||
#define TIMER32_CH_CNTRL_INVERTED_PWM_S 8
|
||||
#define TIMER32_CH_CNTRL_INVERTED_PWM_M (1 << TIMER32_CH_CNTRL_INVERTED_PWM_S)
|
||||
//
|
||||
#define TIMER32_CH_CNTRL_DIR_S 9
|
||||
#define TIMER32_CH_CNTRL_DIR_M (1 << TIMER32_CH_CNTRL_DIR_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CNTRL;
|
||||
volatile uint32_t OCR;
|
||||
volatile uint32_t ICR;
|
||||
volatile uint32_t reserved0;
|
||||
} TIMER32_CHANNEL_TypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t VALUE; /* Offset: 0x000 (R) */
|
||||
volatile uint32_t TOP; /* Offset: 0x004 (R/W) */
|
||||
volatile uint32_t PRESCALER; /* Offset: 0x008 (R/W) */
|
||||
volatile uint32_t CONTROL; /* Offset: 0x00C (R/W) */
|
||||
volatile uint32_t ENABLE; /* Offset: 0x010 (R/W) */
|
||||
volatile uint32_t INT_MASK; /* Offset: 0x014 (R/W) */
|
||||
volatile uint32_t INT_CLEAR; /* Offset: 0x018 (R/W) */
|
||||
volatile uint32_t INT_FLAGS; /* Offset: 0x01C (R) */
|
||||
|
||||
volatile uint8_t reserved0[0x60];
|
||||
TIMER32_CHANNEL_TypeDef CHANNELS[4];
|
||||
|
||||
} TIMER32_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // TIMER32_H_INCLUDED
|
||||
@@ -0,0 +1,158 @@
|
||||
#ifndef UART_H_INCLUDED
|
||||
#define UART_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define UART_CONTROL1_M1_S 28
|
||||
#define UART_CONTROL1_M1_M (1 << UART_CONTROL1_M1_S)
|
||||
#define UART_CONTROL1_M0_S 12
|
||||
#define UART_CONTROL1_M0_M (1 << UART_CONTROL1_M0_S)
|
||||
#define UART_CONTROL1_M_8BIT_M (0)
|
||||
#define UART_CONTROL1_M_9BIT_M (UART_CONTROL1_M0_M)
|
||||
#define UART_CONTROL1_M_7BIT_M (UART_CONTROL1_M1_M)
|
||||
#define UART_CONTROL1_M_M (UART_CONTROL1_M1_M | UART_CONTROL1_M0_M)
|
||||
#define UART_CONTROL1_M(V) (((((v) / 10) << UART_CONTROL1_M1_S) | (((v) % 10) << UART_CONTROL1_M0_S)) & UART_CONTROL1_M_M)
|
||||
#define UART_CONTROL1_PCE_S 10
|
||||
#define UART_CONTROL1_PCE_M (1 << UART_CONTROL1_PCE_S)
|
||||
#define UART_CONTROL1_PS_S 9
|
||||
#define UART_CONTROL1_PS_M (1 << UART_CONTROL1_PS_S)
|
||||
#define UART_CONTROL1_PEIE_S 8
|
||||
#define UART_CONTROL1_PEIE_M (1 << UART_CONTROL1_PEIE_S)
|
||||
#define UART_CONTROL1_TXEIE_S 7
|
||||
#define UART_CONTROL1_TXEIE_M (1 << UART_CONTROL1_TXEIE_S)
|
||||
#define UART_CONTROL1_TCIE_S 6
|
||||
#define UART_CONTROL1_TCIE_M (1 << UART_CONTROL1_TCIE_S)
|
||||
#define UART_CONTROL1_RXNEIE_S 5
|
||||
#define UART_CONTROL1_RXNEIE_M (1 << UART_CONTROL1_RXNEIE_S)
|
||||
#define UART_CONTROL1_IDLEIE_S 4
|
||||
#define UART_CONTROL1_IDLEIE_M (1 << UART_CONTROL1_IDLEIE_S)
|
||||
#define UART_CONTROL1_TE_S 3
|
||||
#define UART_CONTROL1_TE_M (1 << UART_CONTROL1_TE_S)
|
||||
#define UART_CONTROL1_RE_S 2
|
||||
#define UART_CONTROL1_RE_M (1 << UART_CONTROL1_RE_S)
|
||||
#define UART_CONTROL1_UE_S 0
|
||||
#define UART_CONTROL1_UE_M (1 << UART_CONTROL1_UE_S)
|
||||
|
||||
#define UART_CONTROL2_MSBFIRST_S 19
|
||||
#define UART_CONTROL2_MSBFIRST_M (1 << UART_CONTROL2_MSBFIRST_S)
|
||||
#define UART_CONTROL2_DATAINV_S 18
|
||||
#define UART_CONTROL2_DATAINV_M (1 << UART_CONTROL2_DATAINV_S)
|
||||
#define UART_CONTROL2_TXINV_S 17
|
||||
#define UART_CONTROL2_TXINV_M (1 << UART_CONTROL2_TXINV_S)
|
||||
#define UART_CONTROL2_RXINV_S 16
|
||||
#define UART_CONTROL2_RXINV_M (1 << UART_CONTROL2_RXINV_S)
|
||||
#define UART_CONTROL2_SWAP_S 15
|
||||
#define UART_CONTROL2_SWAP_M (1 << UART_CONTROL2_SWAP_S)
|
||||
#define UART_CONTROL2_LBM_S 14
|
||||
#define UART_CONTROL2_LBM_M (1 << UART_CONTROL2_LBM_S)
|
||||
#define UART_CONTROL2_STOP_1_S 13
|
||||
#define UART_CONTROL2_STOP_1_M (1 << UART_CONTROL2_STOP_1_S)
|
||||
#define UART_CONTROL2_CLKEN_S 11
|
||||
#define UART_CONTROL2_CLKEN_M (1 << UART_CONTROL2_CLKEN_S)
|
||||
#define UART_CONTROL2_CPOL_S 10
|
||||
#define UART_CONTROL2_CPOL_M (1 << UART_CONTROL2_CPOL_S)
|
||||
#define UART_CONTROL2_CPHA_S 9
|
||||
#define UART_CONTROL2_CPHA_M (1 << UART_CONTROL2_CPHA_S)
|
||||
#define UART_CONTROL2_LBCL_S 8
|
||||
#define UART_CONTROL2_LBCL_M (1 << UART_CONTROL2_LBCL_S)
|
||||
#define UART_CONTROL2_LBDIE_S 6
|
||||
#define UART_CONTROL2_LBDIE_M (1 << UART_CONTROL2_LBDIE_S)
|
||||
|
||||
#define UART_CONTROL3_OVRDIS_S 12
|
||||
#define UART_CONTROL3_OVRDIS_M (1 << UART_CONTROL3_OVRDIS_S)
|
||||
#define UART_CONTROL3_CTSIE_S 10
|
||||
#define UART_CONTROL3_CTSIE_M (1 << UART_CONTROL3_CTSIE_S)
|
||||
#define UART_CONTROL3_CTSE_S 9
|
||||
#define UART_CONTROL3_CTSE_M (1 << UART_CONTROL3_CTSE_S)
|
||||
#define UART_CONTROL3_RTSE_S 8
|
||||
#define UART_CONTROL3_RTSE_M (1 << UART_CONTROL3_RTSE_S)
|
||||
#define UART_CONTROL3_DMAT_S 7
|
||||
#define UART_CONTROL3_DMAT_M (1 << UART_CONTROL3_DMAT_S)
|
||||
#define UART_CONTROL3_DMAR_S 6
|
||||
#define UART_CONTROL3_DMAR_M (1 << UART_CONTROL3_DMAR_S)
|
||||
#define UART_CONTROL3_HDSEL_S 3
|
||||
#define UART_CONTROL3_HDSEL_M (1 << UART_CONTROL3_HDSEL_S)
|
||||
#define UART_CONTROL3_BKRQ_S 2
|
||||
#define UART_CONTROL3_BKRQ_M (1 << UART_CONTROL3_BKRQ_S)
|
||||
// #define UART_CONTROL3_IREN_S 1
|
||||
// #define UART_CONTROL3_IREN_M (1 << UART_CONTROL3_IREN_S)
|
||||
#define UART_CONTROL3_EIE_S 0
|
||||
#define UART_CONTROL3_EIE_M (1 << UART_CONTROL3_EIE_S)
|
||||
|
||||
#define UART_DIVIDER_BRR_S 0
|
||||
#define UART_DIVIDER_BRR_M (0xFFFF << UART_DIVIDER_BRR_S)
|
||||
|
||||
#define UART_FLAGS_REACK_S 22
|
||||
#define UART_FLAGS_REACK_M (1 << UART_FLAGS_REACK_S)
|
||||
#define UART_FLAGS_TEACK_S 21
|
||||
#define UART_FLAGS_TEACK_M (1 << UART_FLAGS_TEACK_S)
|
||||
#define UART_FLAGS_BUSY_S 16
|
||||
#define UART_FLAGS_BUSY_M (1 << UART_FLAGS_BUSY_S)
|
||||
#define UART_FLAGS_CTS_S 10
|
||||
#define UART_FLAGS_CTS_M (1 << UART_FLAGS_CTS_S)
|
||||
#define UART_FLAGS_CTSIF_S 9
|
||||
#define UART_FLAGS_CTSIF_M (1 << UART_FLAGS_CTSIF_S)
|
||||
#define UART_FLAGS_LBDF_S 8
|
||||
#define UART_FLAGS_LBDF_M (1 << UART_FLAGS_LBDF_S)
|
||||
#define UART_FLAGS_TXE_S 7
|
||||
#define UART_FLAGS_TXE_M (1 << UART_FLAGS_TXE_S)
|
||||
#define UART_FLAGS_TC_S 6
|
||||
#define UART_FLAGS_TC_M (1 << UART_FLAGS_TC_S)
|
||||
#define UART_FLAGS_RXNE_S 5
|
||||
#define UART_FLAGS_RXNE_M (1 << UART_FLAGS_RXNE_S)
|
||||
#define UART_FLAGS_IDLE_S 4
|
||||
#define UART_FLAGS_IDLE_M (1 << UART_FLAGS_IDLE_S)
|
||||
#define UART_FLAGS_ORE_S 3
|
||||
#define UART_FLAGS_ORE_M (1 << UART_FLAGS_ORE_S)
|
||||
#define UART_FLAGS_NF_S 2
|
||||
#define UART_FLAGS_NF_M (1 << UART_FLAGS_NF_S)
|
||||
#define UART_FLAGS_FE_S 1
|
||||
#define UART_FLAGS_FE_M (1 << UART_FLAGS_FE_S)
|
||||
#define UART_FLAGS_PE_S 0
|
||||
#define UART_FLAGS_PE_M (1 << UART_FLAGS_PE_S)
|
||||
|
||||
#define UART_MODEM_DTR_S 8
|
||||
#define UART_MODEM_DTR_M (1 << UART_MODEM_DTR_S)
|
||||
#define UART_MODEM_DCD_S 7
|
||||
#define UART_MODEM_DCD_M (1 << UART_MODEM_DCD_S)
|
||||
#define UART_MODEM_RI_S 6
|
||||
#define UART_MODEM_RI_M (1 << UART_MODEM_RI_S)
|
||||
#define UART_MODEM_DSR_S 5
|
||||
#define UART_MODEM_DSR_M (1 << UART_MODEM_DSR_S)
|
||||
#define UART_MODEM_DCDIF_S 3
|
||||
#define UART_MODEM_DCDIF_M (1 << UART_MODEM_DCDIF_S)
|
||||
#define UART_MODEM_RIIF_S 2
|
||||
#define UART_MODEM_RIIF_M (1 << UART_MODEM_RIIF_S)
|
||||
#define UART_MODEM_DSRIF_S 1
|
||||
#define UART_MODEM_DSRIF_M (1 << UART_MODEM_DSRIF_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CONTROL1;
|
||||
volatile uint32_t CONTROL2;
|
||||
volatile uint32_t CONTROL3;
|
||||
volatile uint32_t DIVIDER;
|
||||
volatile uint32_t _reserved0;
|
||||
volatile uint32_t _reserved1;
|
||||
volatile uint32_t _reserved2;
|
||||
volatile uint32_t FLAGS;
|
||||
volatile uint32_t _reserved3;
|
||||
volatile uint32_t RXDATA;
|
||||
volatile uint32_t TXDATA;
|
||||
volatile uint32_t MODEM;
|
||||
|
||||
} UART_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // UART_H_INCLUDED
|
||||
@@ -0,0 +1,110 @@
|
||||
#ifndef WU_H_INCLUDED
|
||||
#define WU_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define WU_SYS_Mask_OFFSET 0x00
|
||||
#define WU_SYS_Level_OFFSET 0x04
|
||||
#define WU_SYS_PowerOff_OFFSET 0x08
|
||||
#define WU_PowerSwitch_On_Bat_OFFSET 0x0C
|
||||
#define WU_Clocks_OFFSET 0x10
|
||||
#define WU_RTC_Control_OFFSET 0x14
|
||||
#define WU_BOOT 0x28
|
||||
|
||||
|
||||
// SYS_MASK
|
||||
#define WU_MASK_WAKEUP_RTC_S 0
|
||||
#define WU_MASK_WAKEUP_RTC_M (1 << WU_MASK_WAKEUP_RTC_S)
|
||||
#define WU_MASK_WAKEUP_EXT_S 1
|
||||
#define WU_MASK_WAKEUP_EXT_M (1 << WU_MASK_WAKEUP_EXT_S)
|
||||
#define WU_MASK_SYS_RESET_LDO_S 2
|
||||
#define WU_MASK_SYS_RESET_LDO_M (1 << WU_MASK_SYS_RESET_LDO_S)
|
||||
#define WU_MASK_SYS_RESET_VOLTMON_S 3
|
||||
#define WU_MASK_SYS_RESET_VOLTMON_M (1 << WU_MASK_SYS_RESET_VOLTMON_S)
|
||||
#define WU_MASK_SYS_RESET_BOR_S 4
|
||||
#define WU_MASK_SYS_RESET_BOR_M (1 << WU_MASK_SYS_RESET_BOR_S)
|
||||
#define WU_MASK_BU_RESET_BOR_S 5
|
||||
#define WU_MASK_BU_RESET_BOR_M (1 << WU_MASK_BU_RESET_BOR_S)
|
||||
|
||||
// SYS_LEVEL
|
||||
#define WU_SYS_LEVEL_RTC_ALARM_S 0
|
||||
#define WU_SYS_LEVEL_RTC_ALARM_M (0x1 << WU_SYS_LEVEL_RTC_ALARM_S)
|
||||
#define WU_SYS_LEVEL_EXT_LINE_S 1
|
||||
#define WU_SYS_LEVEL_EXT_LINE_M (0x1 << WU_SYS_LEVEL_EXT_LINE_S)
|
||||
|
||||
// SYS_POWEROFF
|
||||
#define WU_SYS_POWEROFF_S 0
|
||||
#define WU_SYS_POWEROFF_M (1 << WU_SYS_POWEROFF_S)
|
||||
|
||||
// POWER_SWITCH
|
||||
#define WU_POWER_SWITCH_EN_S 0
|
||||
#define WU_POWER_SWITCH_EN_M (1 << WU_POWER_SWITCH_EN_S)
|
||||
#define WU_POWER_SWITCH_CONTROL_S 1
|
||||
#define WU_POWER_SWITCH_CONTROL_M (1 << WU_POWER_SWITCH_CONTROL_S)
|
||||
#define WU_POWER_SWITCH_CONTROL_VCC_M (0 << WU_POWER_SWITCH_CONTROL_S)
|
||||
#define WU_POWER_SWITCH_CONTROL_VCC_BU_M (1 << WU_POWER_SWITCH_CONTROL_S)
|
||||
#define WU_POWER_SWITCH_BATT_GOOD_S 2
|
||||
#define WU_POWER_SWITCH_BATT_GOOD_M (1 << WU_POWER_SWITCH_BATT_GOOD_S)
|
||||
|
||||
//CLOCKS_BU
|
||||
#define WU_CLOCKS_BU_OSC32K_EN_S 0
|
||||
#define WU_CLOCKS_BU_OSC32K_EN_M (1 << WU_CLOCKS_BU_OSC32K_EN_S)
|
||||
#define WU_CLOCKS_BU_LSI32K_EN_S 1
|
||||
#define WU_CLOCKS_BU_LSI32K_EN_M (1 << WU_CLOCKS_BU_LSI32K_EN_S)
|
||||
#define WU_CLOCKS_BU_ADJ_LSI32K_S 2
|
||||
#define WU_CLOCKS_BU_ADJ_LSI32K_M (0xFF << WU_CLOCKS_BU_ADJ_LSI32K_S)
|
||||
#define WU_CLOCKS_BU_ADJ_LSI32K(v) (((v) << WU_CLOCKS_BU_ADJ_LSI32K_S) & WU_CLOCKS_BU_ADJ_LSI32K_M)
|
||||
#define WU_CLOCKS_BU_RTC_CLK_MUX_S 10
|
||||
#define WU_CLOCKS_BU_RTC_CLK_MUX_M (0x3 << WU_CLOCKS_BU_RTC_CLK_MUX_S)
|
||||
#define WU_CLOCKS_BU_RTC_CLK_MUX_LSI32K_M (0x1 << WU_CLOCKS_BU_RTC_CLK_MUX_S)
|
||||
#define WU_CLOCKS_BU_RTC_CLK_MUX_OSC32K_M (0x2 << WU_CLOCKS_BU_RTC_CLK_MUX_S)
|
||||
#define WU_CLOCKS_BU_OSC32K_SM_S 14
|
||||
#define WU_CLOCKS_BU_OSC32K_SM_M (1 << WU_CLOCKS_BU_OSC32K_SM_S)
|
||||
|
||||
// CLOCKS_SYS
|
||||
#define WU_CLOCKS_SYS_OSC32M_EN_S 0
|
||||
#define WU_CLOCKS_SYS_OSC32M_EN_M (1 << WU_CLOCKS_SYS_OSC32M_EN_S)
|
||||
#define WU_CLOCKS_SYS_HSI32M_EN_S 1
|
||||
#define WU_CLOCKS_SYS_HSI32M_EN_M (1 << WU_CLOCKS_SYS_HSI32M_EN_S)
|
||||
#define WU_CLOCKS_SYS_ADJ_HSI32M_S 2
|
||||
#define WU_CLOCKS_SYS_ADJ_HSI32M_M (0xFF << WU_CLOCKS_SYS_ADJ_HSI32M_S)
|
||||
#define WU_CLOCKS_SYS_ADJ_HSI32M(v) (((v) << WU_CLOCKS_SYS_ADJ_HSI32M_S) & WU_CLOCKS_SYS_ADJ_HSI32M_M)
|
||||
#define WU_CLOCKS_SYS_FORCE_32K_CLK_S 10
|
||||
#define WU_CLOCKS_SYS_FORCE_32K_CLK_M (0b11 << WU_CLOCKS_SYS_FORCE_32K_CLK_S)
|
||||
#define WU_CLOCKS_SYS_FORCE_32K_CLK_LSI32K_M (0b01 << WU_CLOCKS_SYS_FORCE_32K_CLK_S)
|
||||
#define WU_CLOCKS_SYS_FORCE_32K_CLK_OSC32K_M (0b10 << WU_CLOCKS_SYS_FORCE_32K_CLK_S)
|
||||
|
||||
// RTC_CONRTOL
|
||||
#define WU_RTC_CONTROL_RESET_S 0
|
||||
#define WU_RTC_CONTROL_RESET_SET_M (0 << WU_RTC_CONTROL_RESET_S)
|
||||
#define WU_RTC_CONTROL_RESET_CLEAR_M (1 << WU_RTC_CONTROL_RESET_S)
|
||||
|
||||
// STOP
|
||||
#define WU_STOP_S 0
|
||||
#define WU_STOP_M (1 << WU_STOP_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
typedef struct
|
||||
{
|
||||
|
||||
volatile uint32_t SYS_MASK;
|
||||
volatile uint32_t SYS_LEVEL;
|
||||
volatile uint32_t SYS_POWEROFF;
|
||||
volatile uint32_t POWER_SWITCH;
|
||||
volatile uint32_t CLOCKS_BU;
|
||||
volatile uint32_t CLOCKS_SYS;
|
||||
volatile uint32_t RTC_CONRTOL;
|
||||
volatile uint32_t STOP;
|
||||
} WU_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
#ifndef WDT_H_INCLUDED
|
||||
#define WDT_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define WDT_KEY 0x9C
|
||||
#define WDT_CON 0x84
|
||||
#define WDT_STA 0x9C
|
||||
|
||||
|
||||
#define WDT_KEY_UNLOCK 0x1E
|
||||
#define WDT_KEY_START 0x71
|
||||
#define WDT_KEY_STOP 0xE8
|
||||
|
||||
#define WDT_INTERRUPT_THRESHOLD 0x100
|
||||
|
||||
//CON
|
||||
#define WDT_CON_PRELOAD_S 0
|
||||
#define WDT_CON_PRELOAD_M (0xFFF << WDT_CON_PRELOAD_S)
|
||||
#define WDT_CON_PRELOAD(v) (((v) << WDT_CON_PRELOAD_S) & WDT_CON_PRELOAD_M)
|
||||
//
|
||||
#define WDT_CON_PRESCALE_S 12
|
||||
#define WDT_CON_PRESCALE_M (0x7 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_1_M (0x0 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_2_M (0x1 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_4_M (0x2 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_16_M (0x3 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_64_M (0x4 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_256_M (0x5 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_1024_M (0x6 << WDT_CON_PRESCALE_S)
|
||||
#define WDT_CON_PRESCALE_4096_M (0x7 << WDT_CON_PRESCALE_S)
|
||||
//STA
|
||||
#define WDT_STA_ENABLED_S 0
|
||||
#define WDT_STA_ENABLED_M (1 << WDT_STA_ENABLED_S)
|
||||
#define WDT_STA_LOADING_S 1
|
||||
#define WDT_STA_LOADING_M (1 << WDT_STA_LOADING_S)
|
||||
#define WDT_STA_RST_FLAG_S 8
|
||||
#define WDT_STA_RST_FLAG_M (1 << WDT_STA_RST_FLAG_S)
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
volatile uint8_t _space_Key[WDT_KEY];
|
||||
volatile uint8_t KEY;
|
||||
};
|
||||
struct
|
||||
{
|
||||
volatile uint8_t _space_Con[WDT_CON];
|
||||
volatile uint32_t CON;
|
||||
};
|
||||
struct
|
||||
{
|
||||
volatile uint8_t _space_Sta[WDT_STA];
|
||||
volatile uint32_t STA;
|
||||
};
|
||||
};
|
||||
} WDT_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // WDT_H_INCLUDED
|
||||
@@ -0,0 +1,30 @@
|
||||
#ifndef WDT_BUS_H_INCLUDED
|
||||
#define WDT_BUS_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define WDT_BUS_EEPROM_S 2
|
||||
#define WDT_BUS_SPIFI_S 1
|
||||
#define WDT_BUS_DOM3_S 0
|
||||
|
||||
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
#include <inttypes.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t TIMEOUT;
|
||||
volatile uint32_t INT_CLEAR;
|
||||
volatile uint32_t ENABLE;
|
||||
} WDT_BUS_TypeDef;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // OTP_H_INCLUDED
|
||||
|
||||
@@ -0,0 +1,136 @@
|
||||
|
||||
#define EXCEPTION_STACK_SPACE 32*4
|
||||
#define EXCEPTION_SAVED_REGISTERS 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
|
||||
|
||||
.globl _start, main
|
||||
.weak SmallSystemInit, SystemInit
|
||||
|
||||
.globl trap_entry
|
||||
.globl trap_handler
|
||||
.globl raw_trap_handler
|
||||
.weak trap_handler, raw_trap_handler
|
||||
|
||||
.altmacro
|
||||
.macro memcpy src_beg, src_end, dst, tmp_reg
|
||||
LOCAL memcpy_1, memcpy_2
|
||||
j memcpy_2
|
||||
memcpy_1:
|
||||
lw \tmp_reg, (\src_beg)
|
||||
sw \tmp_reg, (\dst)
|
||||
add \src_beg, \src_beg, 4
|
||||
add \dst, \dst, 4
|
||||
memcpy_2:
|
||||
bltu \src_beg, \src_end, memcpy_1
|
||||
.endm
|
||||
|
||||
.macro memset dst_beg, dst_end, val_reg
|
||||
LOCAL memset_1, memset_2
|
||||
j memset_2
|
||||
memset_1:
|
||||
sw \val_reg, (\dst_beg)
|
||||
add \dst_beg, \dst_beg, 4
|
||||
memset_2:
|
||||
bltu \dst_beg, \dst_end, memset_1
|
||||
.endm
|
||||
|
||||
|
||||
# la uses PC relative addressing (auipc instruction)
|
||||
# Explicit absolut addressing with lui instruction is used
|
||||
# to allow startup code to be executed from any PC address
|
||||
# (la instruction equivalents are left in comments)
|
||||
|
||||
.macro la_abs reg, address
|
||||
.option push
|
||||
.option norelax
|
||||
lui \reg, %hi(\address)
|
||||
addi \reg, \reg, %lo(\address)
|
||||
.option pop
|
||||
.endm
|
||||
|
||||
|
||||
.macro jalr_abs return_reg, address
|
||||
.option push
|
||||
.option norelax
|
||||
lui \return_reg, %hi(\address)
|
||||
jalr \return_reg, %lo(\address)(\return_reg)
|
||||
.option pop
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
.text
|
||||
|
||||
_start:
|
||||
|
||||
# Init stack and global pointer
|
||||
#
|
||||
la_abs sp, __C_STACK_TOP__
|
||||
la_abs gp, _gp
|
||||
|
||||
# Init data
|
||||
#
|
||||
la_abs a1, __DATA_IMAGE_START__
|
||||
la_abs a2, __DATA_IMAGE_END__
|
||||
la_abs a3, __DATA_START__
|
||||
memcpy a1, a2, a3, t0
|
||||
|
||||
# Clear bss
|
||||
#
|
||||
la_abs a1, __BSS_START__
|
||||
la_abs a2, __BSS_END__
|
||||
memset a1, a2, zero
|
||||
|
||||
#ifdef MIK32V0
|
||||
# Enable pad_config clocking
|
||||
#
|
||||
li t0, (1 << 3)
|
||||
li t1, 0x50014
|
||||
sw t0, (t1)
|
||||
#endif
|
||||
|
||||
jalr_abs ra, SmallSystemInit
|
||||
jalr_abs ra, SystemInit
|
||||
|
||||
jalr_abs ra, __libc_init_array
|
||||
jalr_abs ra, main
|
||||
jalr_abs ra, __libc_fini_array
|
||||
|
||||
1: wfi
|
||||
j 1b
|
||||
|
||||
|
||||
// Actions before main: none by default
|
||||
// (weak symbol here - may be redefined)
|
||||
SmallSystemInit:
|
||||
SystemInit:
|
||||
ret
|
||||
|
||||
.section .trap_text, "ax"
|
||||
// .org should be consistent with
|
||||
// default mtvec value (set in scr1_arch_description.svh)
|
||||
//.org 0xC0
|
||||
trap_entry:
|
||||
j raw_trap_handler
|
||||
|
||||
raw_trap_handler:
|
||||
// Save registers
|
||||
addi sp, sp, -(EXCEPTION_STACK_SPACE)
|
||||
.irp index, EXCEPTION_SAVED_REGISTERS
|
||||
sw x\index, 4*index(sp)
|
||||
.endr
|
||||
|
||||
// Call handler
|
||||
la ra, trap_handler
|
||||
jalr ra
|
||||
|
||||
// restore registers
|
||||
.irp index, EXCEPTION_SAVED_REGISTERS
|
||||
lw x\index, 4*index(sp)
|
||||
.endr
|
||||
addi sp, sp, EXCEPTION_STACK_SPACE
|
||||
mret
|
||||
|
||||
// Default handler: infinit loop
|
||||
// (weak symbol here - may be redefined)
|
||||
trap_handler:
|
||||
1: j 1b
|
||||
@@ -0,0 +1,288 @@
|
||||
/* An extremely minimalist syscalls.c for newlib
|
||||
* Based on riscv newlib libgloss/riscv/sys_*.c
|
||||
*
|
||||
* Copyright 2019 Clifford Wolf
|
||||
* Copyright 2019 ETH Zürich and University of Bologna
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
|
||||
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
|
||||
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
|
||||
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
|
||||
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
|
||||
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/**********************************************************************//**
|
||||
* @file syscalls.c
|
||||
* @brief Newlib system calls
|
||||
*
|
||||
* @warning UART0 (if available) is used to read/write console data (STDIN, STDOUT, STDERR, ...).
|
||||
*
|
||||
* @note Original source file: https://github.com/openhwgroup/cv32e40p/blob/master/example_tb/core/custom/syscalls.c
|
||||
* @note Original license: SOLDERPAD HARDWARE LICENSE version 0.51
|
||||
* @note More information was derived from: https://interrupt.memfault.com/blog/boostrapping-libc-with-newlib#implementing-newlib
|
||||
**************************************************************************/
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include <sys/timeb.h>
|
||||
#include <sys/times.h>
|
||||
#include <utime.h>
|
||||
#include <newlib.h>
|
||||
#include <unistd.h>
|
||||
#include <errno.h>
|
||||
|
||||
#undef errno
|
||||
extern int errno;
|
||||
|
||||
// defined in sw/common/crt0.S
|
||||
extern const volatile unsigned int __crt0_main_exit;
|
||||
|
||||
/* It turns out that older newlib versions use different symbol names which goes
|
||||
* against newlib recommendations. Anyway this is fixed in later version.
|
||||
*/
|
||||
#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5
|
||||
# define _sbrk sbrk
|
||||
# define _write write
|
||||
# define _close close
|
||||
# define _lseek lseek
|
||||
# define _read read
|
||||
# define _fstat fstat
|
||||
# define _isatty isatty
|
||||
#endif
|
||||
|
||||
// void unimplemented_syscall()
|
||||
// {
|
||||
// if (neorv32_uart0_available()) {
|
||||
// neorv32_uart0_puts("<syscalls.c> Unimplemented system call called!\n");
|
||||
// }
|
||||
// }
|
||||
|
||||
int nanosleep(const struct timespec *rqtp, struct timespec *rmtp)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _access(const char *file, int mode)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _chdir(const char *path)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _chmod(const char *path, mode_t mode)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _chown(const char *path, uid_t owner, gid_t group)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int file)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _execve(const char *name, char *const argv[], char *const env[])
|
||||
{
|
||||
errno = ENOMEM;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _exit(int exit_status)
|
||||
{
|
||||
// jump to crt0's shutdown code
|
||||
//asm volatile ("la t0, __crt0_main_exit \n"
|
||||
// "jr t0 \n");
|
||||
|
||||
while(1); // will never be reached
|
||||
}
|
||||
|
||||
int _faccessat(int dirfd, const char *file, int mode, int flags)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _fork(void)
|
||||
{
|
||||
errno = EAGAIN;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _fstat(int file, struct stat *st)
|
||||
{
|
||||
st->st_mode = S_IFCHR; // all files are "character special files"
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _fstatat(int dirfd, const char *file, struct stat *st, int flags)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _ftime(struct timeb *tp)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
char *_getcwd(char *buf, size_t size)
|
||||
{
|
||||
errno = -ENOSYS;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int _getpid()
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _gettimeofday(struct timeval *tp, void *tzp)
|
||||
{
|
||||
errno = -ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int file)
|
||||
{
|
||||
return (file == STDOUT_FILENO);
|
||||
}
|
||||
|
||||
int _kill(int pid, int sig)
|
||||
{
|
||||
errno = EINVAL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *old_name, const char *new_name)
|
||||
{
|
||||
errno = EMLINK;
|
||||
return -1;
|
||||
}
|
||||
|
||||
off_t _lseek(int file, off_t ptr, int dir)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _lstat(const char *file, struct stat *st)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _open(const char *name, int flags, int mode)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _openat(int dirfd, const char *name, int flags, int mode)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
ssize_t _read(int file, void *ptr, size_t len)
|
||||
{
|
||||
int read_cnt = 0;
|
||||
|
||||
// read everything (STDIN, ...) from NEORV32.UART0 (if available)
|
||||
// if (neorv32_uart0_available()) {
|
||||
// char *char_ptr;
|
||||
// char_ptr = (char *)ptr;
|
||||
// while (len > 0) {
|
||||
// *char_ptr++ = (char)neorv32_uart0_getc();
|
||||
// read_cnt++;
|
||||
// len--;
|
||||
// }
|
||||
// }
|
||||
|
||||
return read_cnt;
|
||||
}
|
||||
|
||||
int _stat(const char *file, struct stat *st)
|
||||
{
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
// errno = ENOSYS;
|
||||
// return -1;
|
||||
}
|
||||
|
||||
long _sysconf(int name)
|
||||
{
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
clock_t _times(struct tms *buf)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *name)
|
||||
{
|
||||
errno = ENOENT;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _utime(const char *path, const struct utimbuf *times)
|
||||
{
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _wait(int *status)
|
||||
{
|
||||
errno = ECHILD;
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
__attribute__((weak))
|
||||
ssize_t _write(int file, const void *ptr, size_t len)
|
||||
{
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
extern char __heap_start[];
|
||||
extern char __heap_end[];
|
||||
static char *brk = &__heap_start[0];
|
||||
|
||||
int _brk(void *addr)
|
||||
{
|
||||
brk = addr;
|
||||
return 0;
|
||||
}
|
||||
uint32_t sbrk_counter = 0;
|
||||
void *_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
char *old_brk = brk;
|
||||
|
||||
if (&__heap_start[0] == &__heap_end[0]) {
|
||||
return NULL;
|
||||
}
|
||||
sbrk_counter++;
|
||||
if ((brk + incr) < &__heap_end[0]) {
|
||||
brk += incr;
|
||||
} else {
|
||||
brk = &__heap_end[0];
|
||||
}
|
||||
return old_brk;
|
||||
}
|
||||
Reference in new issue
Block a user