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https://github.com/MikronMIK32/mik32-uploader.git
synced 2026-01-01 13:37:03 +03:00
90 lines
1.8 KiB
Python
90 lines
1.8 KiB
Python
# --------------------------
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# DMA register offset
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# --------------------------
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from enum import Enum
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DMA_REGS = 0x00040000
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DMA_CONTROL = DMA_REGS + 0x40
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DMA_CHANNEL_SIZEOF = 0x4 * 4
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def DMA_CHANNEL_DESTINATION(i):
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return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*0
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def DMA_CHANNEL_SOURCE(i):
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return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*1
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def DMA_CHANNEL_LEN(i):
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return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*2
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def DMA_CHANNEL_CONFIG(i):
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return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*3
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# --------------------------
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# SPIFI register offset
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# --------------------------
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SPIFI_REGS = 0x00070000
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SPIFI_CONFIG_CTRL = SPIFI_REGS + 0x000
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SPIFI_CONFIG_CMD = SPIFI_REGS + 0x004
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SPIFI_CONFIG_ADDR = SPIFI_REGS + 0x008
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SPIFI_CONFIG_IDATA = SPIFI_REGS + 0x00C
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SPIFI_CONFIG_CLIMIT = SPIFI_REGS + 0x010
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SPIFI_CONFIG_DATA32 = SPIFI_REGS + 0x014
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SPIFI_CONFIG_MCMD = SPIFI_REGS + 0x018
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SPIFI_CONFIG_STAT = SPIFI_REGS + 0x01C
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# --------------------------
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# PM register offset
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# --------------------------
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PM_REGS = 0x000050000
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PM_Clk_AHB_Set_OFFSET = PM_REGS + 0x0C
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PM_Clk_APB_M_Set_OFFSET = PM_REGS + 0x14
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PM_Clk_APB_P_Set_OFFSET = PM_REGS + 0x1C
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# --------------------------
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# WU register offset
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# --------------------------
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WU_REGS = 0x00060000
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WU_CLOCKS_BU_OFFSET = WU_REGS + 0x10
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# --------------------------
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# GPIO register offset
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# --------------------------
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PAD_CONFIG_REGS = 0x00050C00
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class PAD_CONFIG_REGS_V0(Enum):
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PORT_0_CFG = 0x00
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PORT_1_CFG = 0x04
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PORT_2_CFG = 0x08
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PORT_0_DS = 0x0C
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PORT_1_DS = 0x10
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PORT_2_DS = 0x14
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PORT_0_PUD = 0x18
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PORT_1_PUD = 0x1C
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PORT_2_PUD = 0x20
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class PAD_CONFIG_REGS_V2(Enum):
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PORT_0_CFG = 0x00
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PORT_0_DS = 0x04
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PORT_0_PUD = 0x08
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PORT_1_CFG = 0x0C
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PORT_1_DS = 0x10
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PORT_1_PUD = 0x14
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PORT_2_CFG = 0x18
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PORT_2_DS = 0x1C
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PORT_2_PUD = 0x20
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