mirror of
https://github.com/MikronMIK32/mik32-uploader.git
synced 2026-01-01 13:37:03 +03:00
327 lines
10 KiB
Python
327 lines
10 KiB
Python
from enum import Enum
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from typing import Dict, List
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import time
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from tclrpc import TclException
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from tclrpc import OpenOcdTclRpc
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# --------------------------
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# DMA register offset
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# --------------------------
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DMA_REGS_BASE_ADDRESS = 0x00040000
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DMA_CONTROL = DMA_REGS_BASE_ADDRESS + 0x40
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DMA_CHANNEL_SIZEOF = 0x4 * 4
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def DMA_CHANNEL_DESTINATION(i):
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return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*0
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def DMA_CHANNEL_SOURCE(i):
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return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*1
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def DMA_CHANNEL_LEN(i):
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return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*2
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def DMA_CHANNEL_CONFIG(i):
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return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*3
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# --------------------------
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# DMA register fields
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# --------------------------
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DMA_CHANNEL_COUNT = 4
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DMA_CHANNEL_M = ((1 << DMA_CHANNEL_COUNT) - 1)
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# DMA_CONTROL
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DMA_CONTROL_CLEAR_LOCAL_IRQ_S = 0
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DMA_CONTROL_CLEAR_LOCAL_IRQ_M = (
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DMA_CHANNEL_M << DMA_CONTROL_CLEAR_LOCAL_IRQ_S)
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def DMA_CONTROL_CLEAR_LOCAL_IRQ(i):
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return ((1 << (DMA_CONTROL_CLEAR_LOCAL_IRQ_S + (i))) & DMA_CONTROL_CLEAR_LOCAL_IRQ_M)
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_S = (DMA_CHANNEL_COUNT + 0)
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_M = (1 << DMA_CONTROL_CLEAR_GLOBAL_IRQ_S)
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DMA_CONTROL_CLEAR_ERROR_IRQ_S = (DMA_CHANNEL_COUNT + 1)
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DMA_CONTROL_CLEAR_ERROR_IRQ_M = (1 << DMA_CONTROL_CLEAR_ERROR_IRQ_S)
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DMA_CONTROL_GLOBAL_IRQ_ENA_S = (DMA_CHANNEL_COUNT + 2)
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DMA_CONTROL_GLOBAL_IRQ_ENA_M = (1 << DMA_CONTROL_GLOBAL_IRQ_ENA_S)
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DMA_CONTROL_ERROR_IRQ_ENA_S = (DMA_CHANNEL_COUNT + 3)
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DMA_CONTROL_ERROR_IRQ_ENA_M = (1 << DMA_CONTROL_ERROR_IRQ_ENA_S)
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DMA_CONTROL_CURRENT_VALUE_S = (DMA_CHANNEL_COUNT + 4)
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DMA_CONTROL_CURRENT_VALUE_M = (1 << DMA_CONTROL_CURRENT_VALUE_S)
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DMA_CFG_CH_ENABLE_S = 0
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DMA_CFG_CH_ENABLE_M = (1 << DMA_CFG_CH_ENABLE_S)
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DMA_CFG_CH_DISABLE_M = (0 << DMA_CFG_CH_ENABLE_S)
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DMA_CFG_CH_PRIOR_S = 1
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DMA_CFG_CH_PRIOR_M = (0x3 << DMA_CFG_CH_PRIOR_S)
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DMA_CFG_CH_READ_MODE_S = 3
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DMA_CFG_CH_READ_MODE_memory_M = (1 << DMA_CFG_CH_READ_MODE_S)
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DMA_CFG_CH_READ_MODE_periphery_M = (0 << DMA_CFG_CH_READ_MODE_S)
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DMA_CFG_CH_WRITE_MODE_S = 4
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DMA_CFG_CH_WRITE_MODE_memory_M = (1 << DMA_CFG_CH_WRITE_MODE_S)
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DMA_CFG_CH_WRITE_MODE_periphery_M = (0 << DMA_CFG_CH_WRITE_MODE_S)
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DMA_CFG_CH_READ_INCREMENT_S = 5
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DMA_CFG_CH_READ_INCREMENT_M = (1 << DMA_CFG_CH_READ_INCREMENT_S)
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DMA_CFG_CH_READ_no_INCREMENT_M = (0 << DMA_CFG_CH_READ_INCREMENT_S)
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DMA_CFG_CH_READ_INCREMENT_S = 5
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DMA_CFG_CH_READ_INCREMENT_M = (1 << DMA_CFG_CH_READ_INCREMENT_S)
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DMA_CFG_CH_READ_no_INCREMENT_M = (0 << DMA_CFG_CH_READ_INCREMENT_S)
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DMA_CFG_CH_WRITE_INCREMENT_S = 6
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DMA_CFG_CH_WRITE_INCREMENT_M = (1 << DMA_CFG_CH_WRITE_INCREMENT_S)
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DMA_CFG_CH_WRITE_no_INCREMENT_M = (0 << DMA_CFG_CH_WRITE_INCREMENT_S)
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DMA_CFG_CH_READ_SIZE_S = 7
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DMA_CFG_CH_READ_SIZE_byte_M = (0B00 << DMA_CFG_CH_READ_SIZE_S) # байт
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DMA_CFG_CH_READ_SIZE_2byte_M = (0B01 << DMA_CFG_CH_READ_SIZE_S) # полуслово
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DMA_CFG_CH_READ_SIZE_4byte_M = (0B10 << DMA_CFG_CH_READ_SIZE_S) # слово
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DMA_CFG_CH_READ_SIZE_rez_M = (0B11 << DMA_CFG_CH_READ_SIZE_S) # резерв
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DMA_CFG_CH_WRITE_SIZE_S = 9
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DMA_CFG_CH_WRITE_SIZE_byte_M = (0B00 << DMA_CFG_CH_WRITE_SIZE_S) # байт
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DMA_CFG_CH_WRITE_SIZE_2byte_M = (0B01 << DMA_CFG_CH_WRITE_SIZE_S) # полуслово
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DMA_CFG_CH_WRITE_SIZE_4byte_M = (0B10 << DMA_CFG_CH_WRITE_SIZE_S) # слово
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DMA_CFG_CH_WRITE_SIZE_rez_M = (0B11 << DMA_CFG_CH_WRITE_SIZE_S) # резерв
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# Кол-во байт пакетной передачи: 2^Read_burst_size
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DMA_CFG_CH_READ_BURST_SIZE_S = 11
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# Кол-во байт пакетной передачи: 2^Write_burst_size
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DMA_CFG_CH_WRITE_BURST_SIZE_S = 14
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DMA_CFG_CH_READ_REQ_S = 17 # выбор канала чтения
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DMA_CFG_CH_READ_REQ_M = (0xF << DMA_CFG_CH_READ_REQ_S)
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def DMA_CFG_CH_READ_REQ(v):
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return (((v) << DMA_CFG_CH_READ_REQ_S) & DMA_CFG_CH_READ_REQ_M)
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DMA_CFG_CH_WRITE_REQ_S = 21 # выбор канала записи
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DMA_CFG_CH_WRITE_REQ_M = (0xF << DMA_CFG_CH_WRITE_REQ_S)
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def DMA_CFG_CH_WRITE_REQ(v):
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return (((v) << DMA_CFG_CH_WRITE_REQ_S) & DMA_CFG_CH_WRITE_REQ_M)
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DMA_CFG_CH_ACK_READ_S = 25
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DMA_CFG_CH_ACK_READ_M = (1 << DMA_CFG_CH_ACK_READ_S)
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DMA_CFG_CH_ACK_WRITE_S = 26
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DMA_CFG_CH_ACK_WRITE_M = (1 << DMA_CFG_CH_ACK_WRITE_S)
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DMA_STATUS_READY_S = 0
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# ReadStatus. Разрешить читать текущий статус канала
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class CurrentValue(Enum):
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ENABLE = 0 # Текущие значения
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DISABLE = 1 # Значения при настройке
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class ChannelIndex(Enum):
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CHANNEL_0 = 0
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CHANNEL_1 = 1
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CHANNEL_2 = 2
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CHANNEL_3 = 3
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class ChannelPriority(Enum):
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LOW = 0
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MEDIUM = 1
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HIGH = 2
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VERY_HIGH = 3
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class ChannelMode(Enum):
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PERIPHERY = 0
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MEMORY = 1
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class ChannelIncrement(Enum):
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DISABLE = 0
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ENABLE = 1
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class ChannelSize(Enum):
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BYTE = 0
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HALFWORD = 1
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WORD = 1
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class ChannelAck(Enum):
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DISABLE = 0
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ENABLE = 1
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class ChannelRequest(Enum):
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USART_0_REQUEST = 0
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USART_1_REQUEST = 1
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CRYPTO_REQUEST = 2
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SPI_0_REQUEST = 3
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SPI_1_REQUEST = 4
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I2C_0_REQUEST = 5
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I2C_1_REQUEST = 6
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SPIFI_REQUEST = 7
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TIMER32_1_REQUEST = 8
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TIMER32_2_REQUEST = 9
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TIMER32_0_REQUEST = 10
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class DMA_Channel:
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openocd: OpenOcdTclRpc
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write_buffer: int = 0
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channel: ChannelIndex
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priority: ChannelPriority
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read_mode: ChannelMode
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read_increment: ChannelIncrement
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read_size: ChannelSize
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read_ack: ChannelAck
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read_burst_size: int
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read_request: ChannelRequest
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write_mode: ChannelMode
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write_increment: ChannelIncrement
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write_size: ChannelSize
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write_ack: ChannelAck
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write_burst_size: int
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write_request: ChannelRequest
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def __init__(self, openocd: OpenOcdTclRpc):
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self.openocd = openocd
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def set_source(self, source: int):
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self.openocd.write_word(DMA_CHANNEL_SOURCE(1), source)
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def set_destination(self, source: int):
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self.openocd.write_word(DMA_CHANNEL_DESTINATION(1), source)
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def set_length(self, source: int):
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self.openocd.write_word(DMA_CHANNEL_LEN(1), source)
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def set_config(self, source: int):
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self.openocd.write_word(DMA_CHANNEL_CONFIG(1), source)
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def start(
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self,
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source_address: int,
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destination_address: int,
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length: int,
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):
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self.write_buffer |= (DMA_CFG_CH_ENABLE_M
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| (self.priority.value << DMA_CFG_CH_PRIOR_S)
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| (self.read_mode.value << DMA_CFG_CH_READ_MODE_S)
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| (self.read_increment.value << DMA_CFG_CH_READ_INCREMENT_S)
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| (self.read_size.value << DMA_CFG_CH_READ_SIZE_S)
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| (self.read_burst_size << DMA_CFG_CH_READ_BURST_SIZE_S)
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| (self.read_request.value << DMA_CFG_CH_READ_REQ_S)
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| (self.read_ack.value << DMA_CFG_CH_ACK_READ_S)
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| (self.write_mode.value << DMA_CFG_CH_WRITE_MODE_S)
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| (self.write_increment.value << DMA_CFG_CH_WRITE_INCREMENT_S)
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| (self.write_size.value << DMA_CFG_CH_WRITE_SIZE_S)
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| (self.write_burst_size << DMA_CFG_CH_WRITE_BURST_SIZE_S)
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| (self.write_request.value << DMA_CFG_CH_WRITE_REQ_S)
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| (self.write_ack.value << DMA_CFG_CH_ACK_WRITE_S))
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self.openocd.write_memory(DMA_CHANNEL_DESTINATION(1), 32, [destination_address, source_address, length, self.write_buffer])
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class DMA:
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openocd: OpenOcdTclRpc
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current_value: CurrentValue = CurrentValue.ENABLE
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write_buffer: int = 0
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channels: List[DMA_Channel] = []
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def __init__(self, openocd: OpenOcdTclRpc):
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self.openocd = openocd
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self.channels.append(DMA_Channel(self.openocd))
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self.channels.append(DMA_Channel(self.openocd))
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self.channels.append(DMA_Channel(self.openocd))
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self.channels.append(DMA_Channel(self.openocd))
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def init(self):
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self.current_value = CurrentValue.ENABLE
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self.write_buffer = 0
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self.openocd.write_memory(0x40000, 32, [0] * 16)
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self.clear_irq()
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self.set_current_value(self.current_value)
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def set_control(self, control: int):
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if (control > 2**32 or control < 0):
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raise ValueError
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self.openocd.write_word(DMA_CONTROL, control)
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def get_control(self) -> int:
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return self.openocd.read_word(DMA_CONTROL)
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def clear_irq(self):
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self.clear_local_irq()
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self.clear_global_irq()
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self.clear_error_irq()
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def clear_local_irq(self):
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self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M |
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M)
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self.write_buffer |= DMA_CONTROL_CLEAR_LOCAL_IRQ_M
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self.set_control(self.write_buffer)
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self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M |
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M)
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def clear_global_irq(self):
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self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M |
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M)
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self.write_buffer |= DMA_CONTROL_CLEAR_GLOBAL_IRQ_M
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self.set_control(self.write_buffer)
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self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M |
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M)
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def clear_error_irq(self):
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self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M |
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M)
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self.write_buffer |= DMA_CONTROL_CLEAR_ERROR_IRQ_M
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self.set_control(self.write_buffer)
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self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M |
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DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M)
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def set_current_value(self, current_value: CurrentValue):
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self.current_value = current_value
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self.write_buffer &= ~(DMA_CONTROL_CURRENT_VALUE_M)
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self.write_buffer |= current_value.value << DMA_CONTROL_CURRENT_VALUE_S
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self.set_control(self.write_buffer)
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def dma_wait(self, channel: DMA_Channel, timeout: float):
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channel_index = channel.channel.value
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mask = (1 << channel_index) << DMA_STATUS_READY_S
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begin = time.perf_counter()
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while (begin - time.perf_counter()) < timeout:
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if self.get_control() & mask != 0:
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return
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raise Exception
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