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https://github.com/MikronMIK32/mik32-uploader.git
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9bec497601
функции сгруппированы в классы, для spifi улучшено разделение функционала между контроллерами интерфейса и флеш памяти
215 lines
8.5 KiB
Python
215 lines
8.5 KiB
Python
from enum import Enum
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from typing import List, Union
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import time
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from tclrpc import OpenOcdTclRpc
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import mik32_debug_hal.registers.memory_map as mem_map
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import mik32_debug_hal.registers.bitfields.spifi as spifi_fields
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import mik32_debug_hal.dma as dma
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class SPIFI():
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DEFAULT_READ_DATA_COMMAND = 0x03
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class SpifiError(Exception):
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def __init__(self, value):
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self.value = value
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def __str__(self):
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return ("ERROR: " + repr(self.value))
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class Frameform(Enum):
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RESERVED = 0
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OPCODE_NOADDR = 1
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OPCODE_1ADDR = 2
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OPCODE_2ADDR = 3
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OPCODE_3ADDR = 4
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OPCODE_4ADDR = 5
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NOOPCODE_3ADDR = 6
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NOOPCODE_4ADDR = 7
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class Fieldform(Enum):
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ALL_SERIAL = 0
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DATA_PARALLEL = 1
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OPCODE_SERIAL = 2
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ALL_PARALLEL = 3
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class Direction(Enum):
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READ = 0
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WRITE = 1
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INIT_DELAY = 0.001
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TIMEOUT = 1.0
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openocd: OpenOcdTclRpc
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def __init__(self, openocd: OpenOcdTclRpc):
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self.openocd = openocd
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self.init()
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def intrq_clear(self):
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self.openocd.write_word(mem_map.SPIFI_CONFIG_STAT, self.openocd.read_word(mem_map.SPIFI_CONFIG_STAT) |
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spifi_fields.SPIFI_CONFIG_STAT_INTRQ_M)
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def init_periphery(self):
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self.openocd.write_word(mem_map.SPIFI_CONFIG_STAT, self.openocd.read_word(mem_map.SPIFI_CONFIG_STAT) |
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# SPIFI_CONFIG_STAT_INTRQ_M |
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spifi_fields.SPIFI_CONFIG_STAT_RESET_M)
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# openocd.write_word(SPIFI_CONFIG_CTRL, openocd.read_word(
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# SPIFI_CONFIG_CTRL) | (7 << SPIFI_CONFIG_CTRL_SCK_DIV_S))
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self.openocd.write_word(mem_map.SPIFI_CONFIG_ADDR, 0x00)
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self.openocd.write_word(mem_map.SPIFI_CONFIG_IDATA, 0x00)
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self.openocd.write_word(mem_map.SPIFI_CONFIG_CLIMIT, 0x00)
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time.sleep(self.INIT_DELAY)
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def init(self):
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self.init_periphery()
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control = self.openocd.read_word(mem_map.SPIFI_CONFIG_CTRL)
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control |= spifi_fields.SPIFI_CONFIG_CTRL_DMAEN_M
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self.openocd.write_word(mem_map.SPIFI_CONFIG_CTRL, control)
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time.sleep(self.INIT_DELAY)
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def init_memory(self):
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self.openocd.write_word(mem_map.SPIFI_CONFIG_STAT, self.openocd.read_word(mem_map.SPIFI_CONFIG_STAT) |
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spifi_fields.SPIFI_CONFIG_STAT_INTRQ_M |
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spifi_fields.SPIFI_CONFIG_STAT_RESET_M)
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# openocd.write_word(SPIFI_CONFIG_CTRL, openocd.read_word(
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# SPIFI_CONFIG_CTRL) | (7 << SPIFI_CONFIG_CTRL_SCK_DIV_S))
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self.openocd.write_word(mem_map.SPIFI_CONFIG_ADDR, 0x00)
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self.openocd.write_word(mem_map.SPIFI_CONFIG_IDATA, 0x00)
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self.openocd.write_word(mem_map.SPIFI_CONFIG_CLIMIT, 0x00)
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self.openocd.write_word(mem_map.SPIFI_CONFIG_MCMD, (0 << spifi_fields.SPIFI_CONFIG_MCMD_INTLEN_S) |
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(spifi_fields.SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL << spifi_fields.SPIFI_CONFIG_MCMD_FIELDFORM_S) |
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(spifi_fields.SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR << spifi_fields.SPIFI_CONFIG_MCMD_FRAMEFORM_S) |
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(self.DEFAULT_READ_DATA_COMMAND << spifi_fields.SPIFI_CONFIG_MCMD_OPCODE_S))
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time.sleep(self.INIT_DELAY)
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def spifi_wait_intrq_timeout(self, error_message: str):
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time_end = time.perf_counter() + self.TIMEOUT
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while time.perf_counter() < time_end:
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if (self.openocd.read_word(mem_map.SPIFI_CONFIG_STAT) & spifi_fields.SPIFI_CONFIG_STAT_INTRQ_M) != 0:
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return
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raise self.SpifiError(error_message)
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def send_command(
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self,
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cmd: int,
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frameform: Frameform,
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fieldform: Fieldform,
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byte_count=0,
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address=0,
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idata=0,
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cache_limit=0,
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idata_length=0,
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direction=Direction.READ,
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data: List[int] = [],
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dma: Union[dma.DMA, None] = None
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) -> List[int]:
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if (dma is not None) and (direction == self.Direction.WRITE):
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self.openocd.write_memory(0x02003F00, 8, data)
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dma.channels[0].start(
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0x02003F00,
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mem_map.SPIFI_CONFIG_DATA32,
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255
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)
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elif (dma is not None) and (direction == self.Direction.READ):
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dma.channels[1].start(
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mem_map.SPIFI_CONFIG_DATA32,
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0x02003F00,
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255
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)
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self.openocd.write_memory(
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mem_map.SPIFI_CONFIG_ADDR, 32, [address, idata])
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cmd_write_value = ((cmd << spifi_fields.SPIFI_CONFIG_CMD_OPCODE_S) |
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(frameform.value << spifi_fields.SPIFI_CONFIG_CMD_FRAMEFORM_S) |
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(fieldform.value << spifi_fields.SPIFI_CONFIG_CMD_FIELDFORM_S) |
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(byte_count << spifi_fields.SPIFI_CONFIG_CMD_DATALEN_S) |
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(idata_length << spifi_fields.SPIFI_CONFIG_CMD_INTLEN_S) |
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(direction.value << spifi_fields.SPIFI_CONFIG_CMD_DOUT_S))
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self.openocd.write_memory(
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mem_map.SPIFI_CONFIG_CMD, 32, [cmd_write_value])
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if direction == self.Direction.READ:
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out_list = []
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if dma is not None:
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dma.dma_wait(dma.channels[1], 0.1)
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out_list.extend(self.openocd.read_memory(
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0x02003F00, 8, byte_count))
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return out_list
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else:
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for i in range(byte_count):
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out_list.append(self.openocd.read_memory(
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mem_map.SPIFI_CONFIG_DATA32, 8, 1)[0])
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return out_list
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if direction == self.Direction.WRITE:
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if dma is not None:
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dma.dma_wait(dma.channels[0], 0.1)
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else:
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if (byte_count % 4) == 0:
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for i in range(0, byte_count, 4):
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self.openocd.write_memory(mem_map.SPIFI_CONFIG_DATA32, 32, [
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data[i] + data[i+1] * 256 + data[i+2] * 256 * 256 + data[i+3] * 256 * 256 * 256])
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else:
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for i in range(byte_count):
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self.openocd.write_memory(
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mem_map.SPIFI_CONFIG_DATA32, 8, [data[i]])
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return []
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def dma_config(self) -> dma.DMA:
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dma_instance = dma.DMA(self.openocd)
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dma_instance.init()
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dma_instance.channels[0].write_buffer = 0
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dma_instance.channels[0].channel = dma.ChannelIndex.CHANNEL_0
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dma_instance.channels[0].priority = dma.ChannelPriority.VERY_HIGH
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dma_instance.channels[0].read_mode = dma.ChannelMode.MEMORY
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dma_instance.channels[0].read_increment = dma.ChannelIncrement.ENABLE
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dma_instance.channels[0].read_size = dma.ChannelSize.WORD
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dma_instance.channels[0].read_burst_size = 2
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dma_instance.channels[0].read_request = dma.ChannelRequest.SPIFI_REQUEST
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dma_instance.channels[0].read_ack = dma.ChannelAck.DISABLE
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dma_instance.channels[0].write_mode = dma.ChannelMode.PERIPHERY
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dma_instance.channels[0].write_increment = dma.ChannelIncrement.DISABLE
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dma_instance.channels[0].write_size = dma.ChannelSize.WORD
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dma_instance.channels[0].write_burst_size = 2
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dma_instance.channels[0].write_request = dma.ChannelRequest.SPIFI_REQUEST
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dma_instance.channels[0].write_ack = dma.ChannelAck.DISABLE
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dma_instance.channels[1].write_buffer = 0
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dma_instance.channels[1].channel = dma.ChannelIndex.CHANNEL_1
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dma_instance.channels[1].priority = dma.ChannelPriority.VERY_HIGH
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dma_instance.channels[1].write_mode = dma.ChannelMode.MEMORY
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dma_instance.channels[1].write_increment = dma.ChannelIncrement.ENABLE
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dma_instance.channels[1].write_size = dma.ChannelSize.WORD
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dma_instance.channels[1].write_burst_size = 2
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dma_instance.channels[1].write_request = dma.ChannelRequest.SPIFI_REQUEST
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dma_instance.channels[1].write_ack = dma.ChannelAck.DISABLE
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dma_instance.channels[1].read_mode = dma.ChannelMode.PERIPHERY
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dma_instance.channels[1].read_increment = dma.ChannelIncrement.DISABLE
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dma_instance.channels[1].read_size = dma.ChannelSize.WORD
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dma_instance.channels[1].read_burst_size = 2
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dma_instance.channels[1].read_request = dma.ChannelRequest.SPIFI_REQUEST
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dma_instance.channels[1].read_ack = dma.ChannelAck.DISABLE
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return dma_instance
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