mirror of
https://github.com/MikronMIK32/mik32-uploader.git
synced 2026-01-01 13:37:03 +03:00
734 lines
24 KiB
Python
734 lines
24 KiB
Python
from enum import Enum
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from typing import Dict, List, Union
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import time
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from tclrpc import TclException
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from tclrpc import OpenOcdTclRpc
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from mik32_dma import DMA, ChannelMode, ChannelIndex, ChannelAck, ChannelIncrement, ChannelPriority, ChannelRequest, ChannelSize
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# --------------------------
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# SPIFI register offset
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# --------------------------
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SPIFI_REGS_BASE_ADDRESS = 0x00070000
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SPIFI_CONFIG_CTRL = SPIFI_REGS_BASE_ADDRESS + 0x000
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SPIFI_CONFIG_CMD = SPIFI_REGS_BASE_ADDRESS + 0x004
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SPIFI_CONFIG_ADDR = SPIFI_REGS_BASE_ADDRESS + 0x008
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SPIFI_CONFIG_IDATA = SPIFI_REGS_BASE_ADDRESS + 0x00C
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SPIFI_CONFIG_CLIMIT = SPIFI_REGS_BASE_ADDRESS + 0x010
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SPIFI_CONFIG_DATA32 = SPIFI_REGS_BASE_ADDRESS + 0x014
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SPIFI_CONFIG_MCMD = SPIFI_REGS_BASE_ADDRESS + 0x018
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SPIFI_CONFIG_STAT = SPIFI_REGS_BASE_ADDRESS + 0x01C
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# --------------------------
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# SPIFI register fields
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# --------------------------
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# CTRL
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SPIFI_CONFIG_CTRL_TIMEOUT_S = 0
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SPIFI_CONFIG_CTRL_TIMEOUT_M = (0xFFFF << SPIFI_CONFIG_CTRL_TIMEOUT_S)
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def SPIFI_CONFIG_CTRL_TIMEOUT(v):
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return (((v) << SPIFI_CONFIG_CTRL_TIMEOUT_S) & SPIFI_CONFIG_CTRL_TIMEOUT_M)
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SPIFI_CONFIG_CTRL_CSHIGH_S = 16
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SPIFI_CONFIG_CTRL_CSHIGH_M = (0xF << SPIFI_CONFIG_CTRL_CSHIGH_S)
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def SPIFI_CONFIG_CTRL_CSHIGH(v):
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return (((v) << SPIFI_CONFIG_CTRL_CSHIGH_S) & SPIFI_CONFIG_CTRL_CSHIGH_M)
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SPIFI_CONFIG_CTRL_CACHE_EN_S = 20
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SPIFI_CONFIG_CTRL_CACHE_EN_M = (0x1 << SPIFI_CONFIG_CTRL_CACHE_EN_S)
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SPIFI_CONFIG_CTRL_D_CACHE_DIS_S = 21
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SPIFI_CONFIG_CTRL_D_CACHE_DIS_M = (0x1 << SPIFI_CONFIG_CTRL_D_CACHE_DIS_S)
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SPIFI_CONFIG_CTRL_INTEN_S = 22
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SPIFI_CONFIG_CTRL_INTEN_M = (0x1 << SPIFI_CONFIG_CTRL_INTEN_S)
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SPIFI_CONFIG_CTRL_MODE3_S = 23
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SPIFI_CONFIG_CTRL_MODE3_M = (0x1 << SPIFI_CONFIG_CTRL_MODE3_S)
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SPIFI_CONFIG_CTRL_SCK_DIV_S = 24
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SPIFI_CONFIG_CTRL_SCK_DIV_M = (0x7 << SPIFI_CONFIG_CTRL_SCK_DIV_S)
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def SPIFI_CONFIG_CTRL_SCK_DIV(v):
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return (((v) << SPIFI_CONFIG_CTRL_SCK_DIV_S) & SPIFI_CONFIG_CTRL_SCK_DIV_M)
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SPIFI_CONFIG_CTRL_PREFETCH_DIS_S = 27
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SPIFI_CONFIG_CTRL_PREFETCH_DIS_M = (0x1 << SPIFI_CONFIG_CTRL_PREFETCH_DIS_S)
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SPIFI_CONFIG_CTRL_DUAL_S = 28
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SPIFI_CONFIG_CTRL_DUAL_M = (0x1 << SPIFI_CONFIG_CTRL_DUAL_S)
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SPIFI_CONFIG_CTRL_RFCLK_S = 29
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SPIFI_CONFIG_CTRL_RFCLK_M = (0x1 << SPIFI_CONFIG_CTRL_RFCLK_S)
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SPIFI_CONFIG_CTRL_FBCLK_S = 30
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SPIFI_CONFIG_CTRL_FBCLK_M = (0x1 << SPIFI_CONFIG_CTRL_FBCLK_S)
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SPIFI_CONFIG_CTRL_DMAEN_S = 31
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SPIFI_CONFIG_CTRL_DMAEN_M = (0x1 << SPIFI_CONFIG_CTRL_DMAEN_S)
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# CMD
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SPIFI_CONFIG_CMD_DATALEN_S = 0
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SPIFI_CONFIG_CMD_DATALEN_M = (0x3FFF << SPIFI_CONFIG_CMD_DATALEN_S)
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def SPIFI_CONFIG_CMD_DATALEN(v):
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return (((v) << SPIFI_CONFIG_CMD_DATALEN_S) & SPIFI_CONFIG_CMD_DATALEN_M)
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SPIFI_CONFIG_CMD_POLL_S = 14
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SPIFI_CONFIG_CMD_POLL_M = (0x1 << SPIFI_CONFIG_CMD_POLL_S)
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SPIFI_CONFIG_CMD_DOUT_S = 15
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SPIFI_CONFIG_CMD_DOUT_M = (0x1 << SPIFI_CONFIG_CMD_DOUT_S)
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SPIFI_CONFIG_CMD_INTLEN_S = 16
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SPIFI_CONFIG_CMD_INTLEN_M = (0x7 << SPIFI_CONFIG_CMD_INTLEN_S)
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SPIFI_CONFIG_CMD_FIELDFORM_S = 19
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SPIFI_CONFIG_CMD_FIELDFORM_M = (0x3 << SPIFI_CONFIG_CMD_FIELDFORM_S)
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SPIFI_CONFIG_CMD_FRAMEFORM_S = 21
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SPIFI_CONFIG_CMD_FRAMEFORM_M = (0x7 << SPIFI_CONFIG_CMD_FRAMEFORM_S)
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SPIFI_CONFIG_CMD_OPCODE_S = 24
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SPIFI_CONFIG_CMD_OPCODE_M = (0xFF << SPIFI_CONFIG_CMD_OPCODE_S)
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SPIFI_CONFIG_CMD_DATALEN_BUSY_INDEX_S = 0
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SPIFI_CONFIG_CMD_DATALEN_BUSY_DONE_VALUE_S = 3
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SPIFI_CONFIG_CMD_FRAMEFORM_RESERVED = 0
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SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_NOADDR = 1
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SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_1ADDR = 2
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SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_2ADDR = 3
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SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR = 4
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SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_4ADDR = 5
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SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_3ADDR = 6
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SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_4ADDR = 7
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SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL = 0
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SPIFI_CONFIG_CMD_FIELDFORM_DATA_PARALLEL = 1
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SPIFI_CONFIG_CMD_FIELDFORM_OPCODE_SERIAL = 2
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SPIFI_CONFIG_CMD_FIELDFORM_ALL_PARALLEL = 3
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# MCMD
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SPIFI_CONFIG_MCMD_POLL_S = 14
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SPIFI_CONFIG_MCMD_POLL_M = (0x1 << SPIFI_CONFIG_MCMD_POLL_S)
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SPIFI_CONFIG_MCMD_DOUT_S = 15
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SPIFI_CONFIG_MCMD_DOUT_M = (0x1 << SPIFI_CONFIG_MCMD_DOUT_S)
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SPIFI_CONFIG_MCMD_INTLEN_S = 16
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SPIFI_CONFIG_MCMD_INTLEN_M = (0x7 << SPIFI_CONFIG_MCMD_INTLEN_S)
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SPIFI_CONFIG_MCMD_FIELDFORM_S = 19
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SPIFI_CONFIG_MCMD_FIELDFORM_M = (0x3 << SPIFI_CONFIG_MCMD_FIELDFORM_S)
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SPIFI_CONFIG_MCMD_FRAMEFORM_S = 21
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SPIFI_CONFIG_MCMD_FRAMEFORM_M = (0x7 << SPIFI_CONFIG_MCMD_FRAMEFORM_S)
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SPIFI_CONFIG_MCMD_OPCODE_S = 24
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SPIFI_CONFIG_MCMD_OPCODE_M = (0xFF << SPIFI_CONFIG_MCMD_OPCODE_S)
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# STATUS
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SPIFI_CONFIG_STAT_MCINIT_S = 0
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SPIFI_CONFIG_STAT_MCINIT_M = (0x1 << SPIFI_CONFIG_STAT_MCINIT_S)
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SPIFI_CONFIG_STAT_CMD_S = 1
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SPIFI_CONFIG_STAT_CMD_M = (0x1 << SPIFI_CONFIG_STAT_CMD_S)
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SPIFI_CONFIG_STAT_RESET_S = 4
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SPIFI_CONFIG_STAT_RESET_M = (0x1 << SPIFI_CONFIG_STAT_RESET_S)
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SPIFI_CONFIG_STAT_INTRQ_S = 5
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SPIFI_CONFIG_STAT_INTRQ_M = (0x1 << SPIFI_CONFIG_STAT_INTRQ_S)
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SPIFI_CONFIG_STAT_VERSION_S = 24
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SPIFI_CONFIG_STAT_VERSION_M = (0xFF << SPIFI_CONFIG_STAT_VERSION_S)
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# --------------------------
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# Commands
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# --------------------------
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SREG1_BUSY = 1
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READ_LEN = 256
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TIMEOUT = 1000
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CHIP_ERASE_COMMAND = 0xC7
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SECTOR_ERASE_COMMAND = 0x20
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WRITE_ENABLE_COMMAND = 0x06
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WRITE_DISABLE_COMMAND = 0x04
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DISABLE_QPI_COMMAND = 0xFF
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MEM_CONFIG_COMMAND = 0x61
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MEM_CONFIG_VALUE = 0x7F
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READ_DATA_COMMAND = 0x03
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FAST_READ_QUAD_OUTPUT_COMMAND = 0x6B
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READ_SREG1_COMMAND = 0x05
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READ_SREG2_COMMAND = 0x35
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WRITE_SREG_COMMAND = 0x01
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SREG2_QUAD_ENABLE = 9
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SREG2_QUAD_ENABLE_S = (SREG2_QUAD_ENABLE-8)
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SREG2_QUAD_ENABLE_M = 1 << SREG2_QUAD_ENABLE_S
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PAGE_PROGRAM_COMMAND = 0x02
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QUAD_PAGE_PROGRAM_COMMAND = 0x32
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class SREG_Num(Enum):
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SREG1 = 0x00
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SREG2 = 0x30
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def spifi_intrq_clear(openocd: OpenOcdTclRpc):
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openocd.write_word(SPIFI_CONFIG_STAT, openocd.read_word(SPIFI_CONFIG_STAT) |
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SPIFI_CONFIG_STAT_INTRQ_M)
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INIT_DELAY = 0.001
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def spifi_init_periphery(openocd: OpenOcdTclRpc):
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openocd.write_word(SPIFI_CONFIG_STAT, openocd.read_word(SPIFI_CONFIG_STAT) |
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# SPIFI_CONFIG_STAT_INTRQ_M |
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SPIFI_CONFIG_STAT_RESET_M)
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# openocd.write_word(SPIFI_CONFIG_CTRL, openocd.read_word(
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# SPIFI_CONFIG_CTRL) | (7 << SPIFI_CONFIG_CTRL_SCK_DIV_S))
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openocd.write_word(SPIFI_CONFIG_ADDR, 0x00)
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openocd.write_word(SPIFI_CONFIG_IDATA, 0x00)
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openocd.write_word(SPIFI_CONFIG_CLIMIT, 0x00)
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time.sleep(INIT_DELAY)
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def spifi_init(openocd: OpenOcdTclRpc):
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print("MCU clock init", flush=True)
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spifi_init_periphery(openocd)
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control = openocd.read_word(SPIFI_CONFIG_CTRL)
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control |= SPIFI_CONFIG_CTRL_DMAEN_M
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openocd.write_word(SPIFI_CONFIG_CTRL, control)
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time.sleep(INIT_DELAY)
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def spifi_init_memory(openocd: OpenOcdTclRpc):
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openocd.write_word(SPIFI_CONFIG_STAT, openocd.read_word(SPIFI_CONFIG_STAT) |
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SPIFI_CONFIG_STAT_INTRQ_M |
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SPIFI_CONFIG_STAT_RESET_M)
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# openocd.write_word(SPIFI_CONFIG_CTRL, openocd.read_word(
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# SPIFI_CONFIG_CTRL) | (7 << SPIFI_CONFIG_CTRL_SCK_DIV_S))
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openocd.write_word(SPIFI_CONFIG_ADDR, 0x00)
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openocd.write_word(SPIFI_CONFIG_IDATA, 0x00)
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openocd.write_word(SPIFI_CONFIG_CLIMIT, 0x00)
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openocd.write_word(SPIFI_CONFIG_MCMD, (0 << SPIFI_CONFIG_MCMD_INTLEN_S) |
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(SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL << SPIFI_CONFIG_MCMD_FIELDFORM_S) |
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(SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR << SPIFI_CONFIG_MCMD_FRAMEFORM_S) |
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(0x03 << SPIFI_CONFIG_MCMD_OPCODE_S))
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time.sleep(INIT_DELAY)
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def SPIFI_WaitIntrqTimeout(openocd: OpenOcdTclRpc, timeout: int) -> int:
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timeout_inner = timeout
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while timeout_inner:
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timeout_inner -= 1
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if (openocd.read_word(SPIFI_CONFIG_STAT) & SPIFI_CONFIG_STAT_INTRQ_M) != 0:
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return 1
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return 0
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def spifi_wait_intrq_timeout(openocd: OpenOcdTclRpc, error_message: str):
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if SPIFI_WaitIntrqTimeout(openocd, TIMEOUT) == 0:
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raise Exception(error_message)
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return
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class SPIFI_Frameform(Enum):
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RESERVED = 0
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OPCODE_NOADDR = 1
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OPCODE_1ADDR = 2
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OPCODE_2ADDR = 3
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OPCODE_3ADDR = 4
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OPCODE_4ADDR = 5
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NOOPCODE_3ADDR = 6
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NOOPCODE_4ADDR = 7
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class SPIFI_Fieldform(Enum):
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ALL_SERIAL = 0
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DATA_PARALLEL = 1
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OPCODE_SERIAL = 2
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ALL_PARALLEL = 3
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class SPIFI_Direction(Enum):
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READ = 0
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WRITE = 1
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def spifi_send_command(
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openocd: OpenOcdTclRpc,
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cmd: int,
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frameform: SPIFI_Frameform,
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fieldform: SPIFI_Fieldform,
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byte_count=0,
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address=0,
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idata=0,
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cache_limit=0,
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idata_length=0,
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direction=SPIFI_Direction.READ,
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data: List[int] = [],
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dma: Union[DMA, None] = None
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) -> List[int]:
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if (dma is not None) and (direction == SPIFI_Direction.WRITE):
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openocd.write_memory(0x02003F00, 8, data)
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dma.channels[0].start(
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0x02003F00,
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SPIFI_CONFIG_DATA32,
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255
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)
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elif (dma is not None) and (direction == SPIFI_Direction.READ):
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dma.channels[1].start(
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SPIFI_CONFIG_DATA32,
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0x02003F00,
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255
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)
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openocd.write_memory(SPIFI_CONFIG_ADDR, 32, [address, idata])
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# # spifi_intrq_clear(openocd)
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# openocd.write_word(SPIFI_CONFIG_CMD, (cmd << SPIFI_CONFIG_CMD_OPCODE_S) |
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# (frameform.value << SPIFI_CONFIG_CMD_FRAMEFORM_S) |
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# (fieldform.value << SPIFI_CONFIG_CMD_FIELDFORM_S) |
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# (byte_count << SPIFI_CONFIG_CMD_DATALEN_S) |
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# (idata_length << SPIFI_CONFIG_CMD_INTLEN_S) |
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# (direction.value << SPIFI_CONFIG_CMD_DOUT_S))
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# # spifi_wait_intrq_timeout(openocd, "Timeout executing write enable command")
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cmd_write_value = ((cmd << SPIFI_CONFIG_CMD_OPCODE_S) |
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(frameform.value << SPIFI_CONFIG_CMD_FRAMEFORM_S) |
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(fieldform.value << SPIFI_CONFIG_CMD_FIELDFORM_S) |
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(byte_count << SPIFI_CONFIG_CMD_DATALEN_S) |
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(idata_length << SPIFI_CONFIG_CMD_INTLEN_S) |
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(direction.value << SPIFI_CONFIG_CMD_DOUT_S))
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openocd.write_memory(SPIFI_CONFIG_CMD, 32, [cmd_write_value])
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if direction == SPIFI_Direction.READ:
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out_list = []
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if dma is not None:
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dma.dma_wait(dma.channels[1], 0.1)
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out_list.extend(openocd.read_memory(0x02003F00, 8, byte_count))
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return out_list
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else:
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for i in range(byte_count):
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out_list.append(openocd.read_memory(SPIFI_CONFIG_DATA32, 8, 1)[0])
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return out_list
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if direction == SPIFI_Direction.WRITE:
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if dma is not None:
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dma.dma_wait(dma.channels[0], 0.1)
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else:
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if (byte_count % 4) == 0:
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for i in range(0, byte_count, 4):
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openocd.write_memory(SPIFI_CONFIG_DATA32, 32, [
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data[i] + data[i+1] * 256 + data[i+2] * 256 * 256 + data[i+3] * 256 * 256 * 256])
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else:
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for i in range(byte_count):
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openocd.write_memory(SPIFI_CONFIG_DATA32, 8, [data[i]])
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return []
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def spifi_write_enable(openocd: OpenOcdTclRpc):
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spifi_send_command(openocd, WRITE_ENABLE_COMMAND,
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SPIFI_Frameform.OPCODE_NOADDR, SPIFI_Fieldform.ALL_SERIAL)
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def spifi_read_sreg(openocd: OpenOcdTclRpc, sreg: SREG_Num) -> int:
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return spifi_send_command(
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openocd,
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READ_SREG1_COMMAND | sreg.value,
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SPIFI_Frameform.OPCODE_NOADDR,
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SPIFI_Fieldform.ALL_SERIAL,
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byte_count=1
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)[0]
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def spifi_write_sreg(openocd: OpenOcdTclRpc, sreg1: int, sreg2: int):
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spifi_send_command(openocd, 0xFF,
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SPIFI_Frameform.OPCODE_NOADDR, SPIFI_Fieldform.ALL_PARALLEL)
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spifi_write_enable(openocd)
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spifi_send_command(
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openocd,
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WRITE_SREG_COMMAND,
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SPIFI_Frameform.OPCODE_NOADDR,
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SPIFI_Fieldform.ALL_SERIAL,
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byte_count=2,
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direction=SPIFI_Direction.WRITE,
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data=[sreg1, sreg2]
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)
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spifi_wait_busy(openocd)
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def spifi_wait_busy(openocd: OpenOcdTclRpc):
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while 1:
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sreg1 = spifi_read_sreg(openocd, SREG_Num.SREG1)
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if not (sreg1 & SREG1_BUSY):
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break
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def spifi_chip_disable_qpi(openocd: OpenOcdTclRpc):
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#print("Sending 'Disable QPI' command to external flash chip in QPI mode.", flush=True)
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spifi_send_command(openocd, DISABLE_QPI_COMMAND,
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SPIFI_Frameform.OPCODE_NOADDR, SPIFI_Fieldform.ALL_PARALLEL)
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def spifi_chip_erase(openocd: OpenOcdTclRpc):
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print("Chip erase...", flush=True)
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spifi_send_command(openocd, CHIP_ERASE_COMMAND,
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SPIFI_Frameform.OPCODE_NOADDR, SPIFI_Fieldform.ALL_SERIAL)
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def spifi_sector_erase(openocd: OpenOcdTclRpc, address: int):
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print(f"Erase sector {address:#010x}...", flush=True)
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spifi_send_command(openocd, SECTOR_ERASE_COMMAND,
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SPIFI_Frameform.OPCODE_3ADDR, SPIFI_Fieldform.ALL_SERIAL, address=address)
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def spifi_read_data(openocd: OpenOcdTclRpc, address: int, byte_count: int, bin_data: List[int], dma: Union[DMA, None] = None) -> int:
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read_data: List[int] = []
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read_data = spifi_send_command(openocd, READ_DATA_COMMAND, SPIFI_Frameform.OPCODE_3ADDR, SPIFI_Fieldform.ALL_SERIAL, byte_count=byte_count, address=address, dma=dma)
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for i in range(byte_count):
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if read_data[i] != bin_data[i]:
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print(
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f"DATA[{i+address}] = {read_data[i]:#0x} expect {bin_data[i]:#0x}", flush=True)
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# spifi_init_periphery(openocd)
|
|
# read_periph = spifi_send_command(openocd, READ_DATA_COMMAND, SPIFI_Frameform.OPCODE_3ADDR,
|
|
# SPIFI_Fieldform.ALL_SERIAL, byte_count=1, address=(i+address))
|
|
# print(
|
|
# f"DATA[{i+address}] = {read_periph[0]:#0x} expect {bin_data[i]:#0x}", flush=True)
|
|
|
|
return 1
|
|
|
|
return 0
|
|
|
|
|
|
def spifi_page_program(
|
|
openocd: OpenOcdTclRpc,
|
|
ByteAddress: int,
|
|
data: List[int],
|
|
byte_count: int,
|
|
progress: str = "",
|
|
dma: Union[DMA, None] = None
|
|
):
|
|
print(f"Writing Flash page {ByteAddress:#010x}... {progress}", flush=True)
|
|
if byte_count > 256:
|
|
raise Exception("Byte count more than 256")
|
|
|
|
spifi_write_enable(openocd)
|
|
spifi_send_command(openocd, PAGE_PROGRAM_COMMAND, SPIFI_Frameform.OPCODE_3ADDR,
|
|
SPIFI_Fieldform.ALL_SERIAL, byte_count=byte_count, address=ByteAddress,
|
|
idata=0, cache_limit=0, direction=SPIFI_Direction.WRITE, data=data, dma=dma)
|
|
spifi_wait_busy(openocd)
|
|
|
|
|
|
class EraseType(Enum):
|
|
CHIP_ERASE = CHIP_ERASE_COMMAND
|
|
SECTOR_ERASE = SECTOR_ERASE_COMMAND
|
|
|
|
|
|
def spifi_erase(openocd, erase_type: EraseType = EraseType.CHIP_ERASE, sectors: List[int] = []):
|
|
if erase_type == EraseType.CHIP_ERASE:
|
|
spifi_write_enable(openocd)
|
|
spifi_chip_erase(openocd)
|
|
spifi_wait_busy(openocd)
|
|
elif erase_type == EraseType.SECTOR_ERASE:
|
|
for sector in sectors:
|
|
spifi_write_enable(openocd)
|
|
spifi_sector_erase(openocd, sector)
|
|
spifi_wait_busy(openocd)
|
|
|
|
|
|
def spifi_write(openocd: OpenOcdTclRpc, address: int, data: List[int], data_len: int):
|
|
if data_len > 256:
|
|
raise Exception("Byte count more than 256")
|
|
|
|
spifi_page_program(openocd, address, data, data_len)
|
|
|
|
print("written")
|
|
|
|
|
|
def spifi_write_file(bytes: List[int], openocd: OpenOcdTclRpc):
|
|
# print(bytes)
|
|
print(f"Write {len(bytes)} bytes")
|
|
|
|
openocd.halt()
|
|
spifi_init(openocd)
|
|
spifi_erase(openocd)
|
|
print("bin_data_len = ", len(bytes))
|
|
address = 0
|
|
|
|
for address in range(0, len(bytes), 256):
|
|
if ((address + 256) > len(bytes)):
|
|
break
|
|
print("address = ", address)
|
|
spifi_write(openocd, address, bytes, 256)
|
|
if spifi_read_data(openocd, address, 256, bytes) == 1:
|
|
return 1
|
|
|
|
if (len(bytes) % 256) != 0:
|
|
print(
|
|
f"address = {address}, +{len(bytes) - address-1}[{address + len(bytes) - address-1}]")
|
|
spifi_write(openocd, address, bytes, len(bytes) - address)
|
|
if spifi_read_data(openocd, address, len(bytes) - address, bytes) == 1:
|
|
return 1
|
|
print("end")
|
|
|
|
return 0
|
|
|
|
|
|
def spifi_quad_page_program(
|
|
openocd: OpenOcdTclRpc,
|
|
ByteAddress: int,
|
|
data: List[int],
|
|
byte_count: int,
|
|
progress: str = "",
|
|
dma: Union[DMA, None] = None
|
|
):
|
|
print(f"Writing page {ByteAddress:#010x}... {progress}", flush=True)
|
|
if byte_count > 256:
|
|
raise Exception("Byte count more than 256")
|
|
|
|
spifi_write_enable(openocd)
|
|
spifi_send_command(openocd, QUAD_PAGE_PROGRAM_COMMAND, SPIFI_Frameform.OPCODE_3ADDR,
|
|
SPIFI_Fieldform.DATA_PARALLEL, byte_count=byte_count, address=ByteAddress,
|
|
idata=0, cache_limit=0, direction=SPIFI_Direction.WRITE, data=data, dma=dma)
|
|
spifi_wait_busy(openocd)
|
|
|
|
|
|
def spifi_quad_enable(openocd):
|
|
spifi_write_sreg(
|
|
openocd,
|
|
spifi_read_sreg(openocd, SREG_Num.SREG1),
|
|
spifi_read_sreg(openocd, SREG_Num.SREG2) | SREG2_QUAD_ENABLE_M
|
|
)
|
|
|
|
|
|
def spifi_quad_disable(openocd):
|
|
spifi_write_sreg(
|
|
openocd,
|
|
spifi_read_sreg(openocd, SREG_Num.SREG1),
|
|
spifi_read_sreg(openocd, SREG_Num.SREG2) & (0xFF ^ SREG2_QUAD_ENABLE_M)
|
|
)
|
|
|
|
|
|
def spifi_check_quad_enable(openocd):
|
|
return (spifi_read_sreg(openocd, SREG_Num.SREG2) & SREG2_QUAD_ENABLE_M) != 0
|
|
|
|
|
|
def get_segments_list(pages_offsets: List[int], segment_size: int) -> List[int]:
|
|
segments = set()
|
|
for offset in pages_offsets:
|
|
segments.add(offset & ~(segment_size - 1))
|
|
return list(segments)
|
|
|
|
|
|
def check_pages(pages: Dict[int, List[int]], openocd: OpenOcdTclRpc, use_quad_spi=False, use_chip_erase=False):
|
|
result = 0
|
|
|
|
openocd.halt()
|
|
spifi_init(openocd)
|
|
|
|
JEDEC_ID = spifi_send_command(openocd, 0x9F, SPIFI_Frameform.OPCODE_NOADDR, SPIFI_Fieldform.ALL_SERIAL, 3)
|
|
|
|
print(f"JEDEC_ID {JEDEC_ID[0]:02x} {JEDEC_ID[1]:02x} {JEDEC_ID[2]:02x}")
|
|
|
|
dma = DMA(openocd)
|
|
dma.init()
|
|
|
|
dma.channels[0].write_buffer = 0
|
|
|
|
dma.channels[0].channel = ChannelIndex.CHANNEL_0
|
|
dma.channels[0].priority = ChannelPriority.VERY_HIGH
|
|
|
|
dma.channels[0].read_mode = ChannelMode.MEMORY
|
|
dma.channels[0].read_increment = ChannelIncrement.ENABLE
|
|
dma.channels[0].read_size = ChannelSize.WORD
|
|
dma.channels[0].read_burst_size = 2
|
|
dma.channels[0].read_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[0].read_ack = ChannelAck.DISABLE
|
|
|
|
dma.channels[0].write_mode = ChannelMode.PERIPHERY
|
|
dma.channels[0].write_increment = ChannelIncrement.DISABLE
|
|
dma.channels[0].write_size = ChannelSize.WORD
|
|
dma.channels[0].write_burst_size = 2
|
|
dma.channels[0].write_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[0].write_ack = ChannelAck.DISABLE
|
|
|
|
dma.channels[1].write_buffer = 0
|
|
|
|
dma.channels[1].channel = ChannelIndex.CHANNEL_1
|
|
dma.channels[1].priority = ChannelPriority.VERY_HIGH
|
|
|
|
dma.channels[1].write_mode = ChannelMode.MEMORY
|
|
dma.channels[1].write_increment = ChannelIncrement.ENABLE
|
|
dma.channels[1].write_size = ChannelSize.WORD
|
|
dma.channels[1].write_burst_size = 2
|
|
dma.channels[1].write_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[1].write_ack = ChannelAck.DISABLE
|
|
|
|
dma.channels[1].read_mode = ChannelMode.PERIPHERY
|
|
dma.channels[1].read_increment = ChannelIncrement.DISABLE
|
|
dma.channels[1].read_size = ChannelSize.WORD
|
|
dma.channels[1].read_burst_size = 2
|
|
dma.channels[1].read_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[1].read_ack = ChannelAck.DISABLE
|
|
|
|
if (use_quad_spi):
|
|
print("Quad Enable")
|
|
spifi_quad_enable(openocd)
|
|
else:
|
|
spifi_quad_disable(openocd)
|
|
|
|
pages_offsets = list(pages)
|
|
|
|
for index, page_offset in enumerate(pages_offsets):
|
|
print(f"Check page {page_offset:#010x}... {(index*100)//pages_offsets.__len__()}%", flush=True)
|
|
page_bytes = pages[page_offset]
|
|
|
|
result = spifi_read_data(openocd, page_offset, 256, page_bytes, dma=dma)
|
|
|
|
if result == 1:
|
|
print("Data error")
|
|
if (use_quad_spi):
|
|
spifi_quad_disable(openocd)
|
|
return result
|
|
|
|
if result == 0:
|
|
print("SPIFI pages checking completed", flush=True)
|
|
return 0
|
|
|
|
# # PROFILING IMPORTS
|
|
# import cProfile, pstats, io
|
|
# from pstats import SortKey
|
|
|
|
def write_pages(pages: Dict[int, List[int]], openocd: OpenOcdTclRpc, use_quad_spi=False, use_chip_erase=False):
|
|
result = 0
|
|
|
|
# # PROFILING INIT
|
|
# pr = cProfile.Profile()
|
|
# pr.enable()
|
|
# # PROFILING INIT END
|
|
|
|
openocd.halt()
|
|
spifi_init(openocd)
|
|
|
|
# Выводим микросхему из режима QPI, так как SPIFI здесь будет работать в режиме SPI.
|
|
spifi_chip_disable_qpi(openocd)
|
|
|
|
JEDEC_ID = spifi_send_command(openocd, 0x9F, SPIFI_Frameform.OPCODE_NOADDR, SPIFI_Fieldform.ALL_SERIAL, 3)
|
|
|
|
print(f"JEDEC_ID {JEDEC_ID[0]:02x} {JEDEC_ID[1]:02x} {JEDEC_ID[2]:02x}")
|
|
|
|
dma = DMA(openocd)
|
|
dma.init()
|
|
|
|
dma.channels[0].write_buffer = 0
|
|
|
|
dma.channels[0].channel = ChannelIndex.CHANNEL_0
|
|
dma.channels[0].priority = ChannelPriority.VERY_HIGH
|
|
|
|
dma.channels[0].read_mode = ChannelMode.MEMORY
|
|
dma.channels[0].read_increment = ChannelIncrement.ENABLE
|
|
dma.channels[0].read_size = ChannelSize.WORD
|
|
dma.channels[0].read_burst_size = 2
|
|
dma.channels[0].read_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[0].read_ack = ChannelAck.DISABLE
|
|
|
|
dma.channels[0].write_mode = ChannelMode.PERIPHERY
|
|
dma.channels[0].write_increment = ChannelIncrement.DISABLE
|
|
dma.channels[0].write_size = ChannelSize.WORD
|
|
dma.channels[0].write_burst_size = 2
|
|
dma.channels[0].write_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[0].write_ack = ChannelAck.DISABLE
|
|
|
|
dma.channels[1].write_buffer = 0
|
|
|
|
dma.channels[1].channel = ChannelIndex.CHANNEL_1
|
|
dma.channels[1].priority = ChannelPriority.VERY_HIGH
|
|
|
|
dma.channels[1].write_mode = ChannelMode.MEMORY
|
|
dma.channels[1].write_increment = ChannelIncrement.ENABLE
|
|
dma.channels[1].write_size = ChannelSize.WORD
|
|
dma.channels[1].write_burst_size = 2
|
|
dma.channels[1].write_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[1].write_ack = ChannelAck.DISABLE
|
|
|
|
dma.channels[1].read_mode = ChannelMode.PERIPHERY
|
|
dma.channels[1].read_increment = ChannelIncrement.DISABLE
|
|
dma.channels[1].read_size = ChannelSize.WORD
|
|
dma.channels[1].read_burst_size = 2
|
|
dma.channels[1].read_request = ChannelRequest.SPIFI_REQUEST
|
|
dma.channels[1].read_ack = ChannelAck.DISABLE
|
|
|
|
if use_chip_erase:
|
|
spifi_erase(openocd, EraseType.CHIP_ERASE)
|
|
else:
|
|
spifi_erase(openocd, EraseType.SECTOR_ERASE,
|
|
get_segments_list(list(pages), 4*1024))
|
|
|
|
# for addr in range(0, 4096*2, 256):
|
|
# result = spifi_read_data(openocd, addr, 256, [0xFF]*256, dma=dma)
|
|
|
|
# if result == 1:
|
|
# print("Data error")
|
|
# return result
|
|
|
|
print("Quad Enable", spifi_check_quad_enable(openocd))
|
|
|
|
if (use_quad_spi):
|
|
print("Using Quad SPI")
|
|
spifi_quad_enable(openocd)
|
|
else:
|
|
print("Using Single SPI")
|
|
spifi_quad_disable(openocd)
|
|
|
|
# print("SREG1", spifi_read_sreg(openocd, SREG_Num.SREG1))
|
|
# print("SREG2", spifi_read_sreg(openocd, SREG_Num.SREG2))
|
|
|
|
pages_offsets = list(pages)
|
|
|
|
for index, page_offset in enumerate(pages_offsets):
|
|
page_bytes = pages[page_offset]
|
|
|
|
if (use_quad_spi):
|
|
spifi_quad_page_program(
|
|
openocd, page_offset, page_bytes, 256, f"{(index*100)//pages_offsets.__len__()}%", dma=dma)
|
|
else:
|
|
spifi_page_program(openocd, page_offset, page_bytes,
|
|
256, f"{(index*100)//pages_offsets.__len__()}%", dma=dma)
|
|
|
|
result = spifi_read_data(openocd, page_offset, 256, page_bytes, dma=dma)
|
|
|
|
if result == 1:
|
|
print("Data error")
|
|
return result
|
|
|
|
if (use_quad_spi):
|
|
spifi_quad_disable(openocd)
|
|
|
|
# # PROFILING GET STATS
|
|
# pr.disable()
|
|
# s = io.StringIO()
|
|
# sortby = SortKey.CUMULATIVE
|
|
# ps = pstats.Stats(pr, stream=s).sort_stats(sortby)
|
|
# ps.print_stats()
|
|
# print(s.getvalue())
|
|
# # PROFILING GET STATS END
|
|
|
|
if result == 0:
|
|
# Прошивка страниц флеш памяти по SPIFI была завершена
|
|
print("Flashing of flash memory pages via SPIFI has been completed", flush=True)
|
|
return 0
|