diff --git a/CHANGELOG.md b/CHANGELOG.md index c607180..ad4d685 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,6 +17,8 @@ ### Добавлено ### Изменено +- [Перенос драйверов и регистров в модуль]() + Драйверы, смещения и маски регистров и битовых полей перенесены в модуль mik32_debug_hal ### Исправлено diff --git a/mik32_check.py b/mik32_check.py index 5096b1d..603a442 100644 --- a/mik32_check.py +++ b/mik32_check.py @@ -6,12 +6,12 @@ import sys import time from typing import List, Union -from mik32_pm import pm_init +from mik32_debug_hal.power_manager import pm_init from mik32_upload import BootMode, Pages, form_pages, openocd_exec_path, openocd_scripts_path, openocd_interface_path, openocd_target_path, adapter_default_speed, run_openocd, default_post_action, default_log_path, default_openocd_host, mik32v0_sections, OpenOCDStartupException, adapter_speed_not_supported, memory_page_size -from mik32_gpio import MIK32_Version, gpio_init, gpio_deinit -import mik32_eeprom -import mik32_spifi -import mik32_ram +from mik32_debug_hal.gpio import MIK32_Version, gpio_init, gpio_deinit +import mik32_debug_hal.eeprom as eeprom +import mik32_debug_hal.spifi as spifi +import mik32_debug_hal.ram as ram from hex_parser import FirmwareFile, MemoryType, Segment from tclrpc import OpenOcdTclRpc, TclException @@ -80,7 +80,7 @@ def upload_file( if (pages.pages_eeprom.__len__() > 0): start_time = time.perf_counter() - result |= mik32_eeprom.check_pages( + result |= eeprom.check_pages( pages.pages_eeprom, openocd) write_time = time.perf_counter() - start_time @@ -92,7 +92,7 @@ def upload_file( gpio_init(openocd, mik_version) start_time = time.perf_counter() - result |= mik32_spifi.check_pages( + result |= spifi.check_pages( pages.pages_spifi, openocd, use_quad_spi=use_quad_spi) write_time = time.perf_counter() - start_time @@ -105,7 +105,7 @@ def upload_file( segments_ram = list(filter( lambda segment: (segment.memory is not None) and (segment.memory.type == MemoryType.RAM), segments)) if (segments_ram.__len__() > 0): - mik32_ram.check_segments(segments_ram, openocd) + ram.check_segments(segments_ram, openocd) result |= 0 openocd.run(post_action) diff --git a/mik32_debug_hal/dma.py b/mik32_debug_hal/dma.py new file mode 100644 index 0000000..48d640d --- /dev/null +++ b/mik32_debug_hal/dma.py @@ -0,0 +1,204 @@ +from enum import Enum +from typing import Dict, List +import time +from tclrpc import TclException +from tclrpc import OpenOcdTclRpc +from dataclasses import dataclass +import mik32_debug_hal.registers.memory_map as mem_map +import mik32_debug_hal.registers.bitfields.dma as dma_fields + +# ReadStatus. Разрешить читать текущий статус канала +class CurrentValue(Enum): + ENABLE = 0 # Текущие значения + DISABLE = 1 # Значения при настройке + + +class ChannelIndex(Enum): + CHANNEL_0 = 0 + CHANNEL_1 = 1 + CHANNEL_2 = 2 + CHANNEL_3 = 3 + + +class ChannelPriority(Enum): + LOW = 0 + MEDIUM = 1 + HIGH = 2 + VERY_HIGH = 3 + + +class ChannelMode(Enum): + PERIPHERY = 0 + MEMORY = 1 + + +class ChannelIncrement(Enum): + DISABLE = 0 + ENABLE = 1 + + +class ChannelSize(Enum): + BYTE = 0 + HALFWORD = 1 + WORD = 1 + + +class ChannelAck(Enum): + DISABLE = 0 + ENABLE = 1 + + +class ChannelRequest(Enum): + USART_0_REQUEST = 0 + USART_1_REQUEST = 1 + CRYPTO_REQUEST = 2 + SPI_0_REQUEST = 3 + SPI_1_REQUEST = 4 + I2C_0_REQUEST = 5 + I2C_1_REQUEST = 6 + SPIFI_REQUEST = 7 + TIMER32_1_REQUEST = 8 + TIMER32_2_REQUEST = 9 + TIMER32_0_REQUEST = 10 + + +class DMA_Channel: + openocd: OpenOcdTclRpc + + write_buffer: int = 0 + + channel: ChannelIndex + priority: ChannelPriority + + read_mode: ChannelMode + read_increment: ChannelIncrement + read_size: ChannelSize + read_ack: ChannelAck + read_burst_size: int + read_request: ChannelRequest + + write_mode: ChannelMode + write_increment: ChannelIncrement + write_size: ChannelSize + write_ack: ChannelAck + write_burst_size: int + write_request: ChannelRequest + + def __init__(self, openocd: OpenOcdTclRpc): + self.openocd = openocd + + def set_source(self, source: int): + self.openocd.write_word(mem_map.DMA_CHANNEL_SOURCE(1), source) + + def set_destination(self, source: int): + self.openocd.write_word(mem_map.DMA_CHANNEL_DESTINATION(1), source) + + def set_length(self, source: int): + self.openocd.write_word(mem_map.DMA_CHANNEL_LEN(1), source) + + def set_config(self, source: int): + self.openocd.write_word(mem_map.DMA_CHANNEL_CONFIG(1), source) + + def start( + self, + source_address: int, + destination_address: int, + length: int, + ): + self.write_buffer |= (dma_fields.CFG_CH_ENABLE_M + | (self.priority.value << dma_fields.CFG_CH_PRIOR_S) + | (self.read_mode.value << dma_fields.CFG_CH_READ_MODE_S) + | (self.read_increment.value << dma_fields.CFG_CH_READ_INCREMENT_S) + | (self.read_size.value << dma_fields.CFG_CH_READ_SIZE_S) + | (self.read_burst_size << dma_fields.CFG_CH_READ_BURST_SIZE_S) + | (self.read_request.value << dma_fields.CFG_CH_READ_REQ_S) + | (self.read_ack.value << dma_fields.CFG_CH_ACK_READ_S) + | (self.write_mode.value << dma_fields.CFG_CH_WRITE_MODE_S) + | (self.write_increment.value << dma_fields.CFG_CH_WRITE_INCREMENT_S) + | (self.write_size.value << dma_fields.CFG_CH_WRITE_SIZE_S) + | (self.write_burst_size << dma_fields.CFG_CH_WRITE_BURST_SIZE_S) + | (self.write_request.value << dma_fields.CFG_CH_WRITE_REQ_S) + | (self.write_ack.value << dma_fields.CFG_CH_ACK_WRITE_S)) + + self.openocd.write_memory(mem_map.DMA_CHANNEL_DESTINATION( + 1), 32, [destination_address, source_address, length, self.write_buffer]) + + +class DMA: + openocd: OpenOcdTclRpc + + current_value: CurrentValue = CurrentValue.ENABLE + write_buffer: int = 0 + + channels: List[DMA_Channel] = [] + + def __init__(self, openocd: OpenOcdTclRpc): + self.openocd = openocd + self.channels.append(DMA_Channel(self.openocd)) + self.channels.append(DMA_Channel(self.openocd)) + self.channels.append(DMA_Channel(self.openocd)) + self.channels.append(DMA_Channel(self.openocd)) + + def init(self): + self.current_value = CurrentValue.ENABLE + + self.write_buffer = 0 + self.openocd.write_memory(0x40000, 32, [0] * 16) + self.clear_irq() + self.set_current_value(self.current_value) + + def set_control(self, control: int): + if (control > 2**32 or control < 0): + raise ValueError + + self.openocd.write_word(mem_map.DMA_CONTROL, control) + + def get_control(self) -> int: + return self.openocd.read_word(mem_map.DMA_CONTROL) + + def clear_irq(self): + self.clear_local_irq() + self.clear_global_irq() + self.clear_error_irq() + + def clear_local_irq(self): + self.write_buffer &= ~(dma_fields.CONTROL_CLEAR_LOCAL_IRQ_M | + dma_fields.CONTROL_CLEAR_GLOBAL_IRQ_M | dma_fields.CONTROL_CLEAR_ERROR_IRQ_M) + self.write_buffer |= dma_fields.CONTROL_CLEAR_LOCAL_IRQ_M + self.set_control(self.write_buffer) + self.write_buffer &= ~(dma_fields.CONTROL_CLEAR_LOCAL_IRQ_M | + dma_fields.CONTROL_CLEAR_GLOBAL_IRQ_M | dma_fields.CONTROL_CLEAR_ERROR_IRQ_M) + + def clear_global_irq(self): + self.write_buffer &= ~(dma_fields.CONTROL_CLEAR_LOCAL_IRQ_M | + dma_fields.CONTROL_CLEAR_GLOBAL_IRQ_M | dma_fields.CONTROL_CLEAR_ERROR_IRQ_M) + self.write_buffer |= dma_fields.CONTROL_CLEAR_GLOBAL_IRQ_M + self.set_control(self.write_buffer) + self.write_buffer &= ~(dma_fields.CONTROL_CLEAR_LOCAL_IRQ_M | + dma_fields.CONTROL_CLEAR_GLOBAL_IRQ_M | dma_fields.CONTROL_CLEAR_ERROR_IRQ_M) + + def clear_error_irq(self): + self.write_buffer &= ~(dma_fields.CONTROL_CLEAR_LOCAL_IRQ_M | + dma_fields.CONTROL_CLEAR_GLOBAL_IRQ_M | dma_fields.CONTROL_CLEAR_ERROR_IRQ_M) + self.write_buffer |= dma_fields.CONTROL_CLEAR_ERROR_IRQ_M + self.set_control(self.write_buffer) + self.write_buffer &= ~(dma_fields.CONTROL_CLEAR_LOCAL_IRQ_M | + dma_fields.CONTROL_CLEAR_GLOBAL_IRQ_M | dma_fields.CONTROL_CLEAR_ERROR_IRQ_M) + + def set_current_value(self, current_value: CurrentValue): + self.current_value = current_value + self.write_buffer &= ~(dma_fields.CONTROL_CURRENT_VALUE_M) + self.write_buffer |= current_value.value << dma_fields.CONTROL_CURRENT_VALUE_S + self.set_control(self.write_buffer) + + def dma_wait(self, channel: DMA_Channel, timeout: float): + channel_index = channel.channel.value + mask = (1 << channel_index) << dma_fields.STATUS_READY_S + + begin = time.perf_counter() + + while (begin - time.perf_counter()) < timeout: + if self.get_control() & mask != 0: + return + + raise Exception diff --git a/mik32_eeprom.py b/mik32_debug_hal/eeprom.py similarity index 100% rename from mik32_eeprom.py rename to mik32_debug_hal/eeprom.py diff --git a/mik32_gpio.py b/mik32_debug_hal/gpio.py similarity index 53% rename from mik32_gpio.py rename to mik32_debug_hal/gpio.py index 1ec8f3b..fe4997c 100644 --- a/mik32_gpio.py +++ b/mik32_debug_hal/gpio.py @@ -1,8 +1,6 @@ -# -------------------------- -# PM register offset -# -------------------------- from enum import Enum from tclrpc import OpenOcdTclRpc +import mik32_debug_hal.registers.memory_map as mem_map class MIK32_Version(Enum): @@ -13,31 +11,6 @@ class MIK32_Version(Enum): return self.value -PAD_CONFIG_BASE_ADDRESS = 0x00050C00 - -class PAD_CONFIG_REGS_V0(Enum): - PORT_0_CFG = 0x00 - PORT_1_CFG = 0x04 - PORT_2_CFG = 0x08 - PORT_0_DS = 0x0C - PORT_1_DS = 0x10 - PORT_2_DS = 0x14 - PORT_0_PUD = 0x18 - PORT_1_PUD = 0x1C - PORT_2_PUD = 0x20 - -class PAD_CONFIG_REGS_V2(Enum): - PORT_0_CFG = 0x00 - PORT_0_DS = 0x04 - PORT_0_PUD = 0x08 - PORT_1_CFG = 0x0C - PORT_1_DS = 0x10 - PORT_1_PUD = 0x14 - PORT_2_CFG = 0x18 - PORT_2_DS = 0x1C - PORT_2_PUD = 0x20 - - port2_value = 0 @@ -45,9 +18,9 @@ def gpio_init(openocd: OpenOcdTclRpc, version: MIK32_Version): port2_addr = 0 if version == MIK32_Version.MIK32V0: - port2_addr = PAD_CONFIG_BASE_ADDRESS + PAD_CONFIG_REGS_V0.PORT_2_CFG.value + port2_addr = mem_map.PAD_CONFIG_REGS + mem_map.PAD_CONFIG_REGS_V0.PORT_2_CFG.value elif version == MIK32_Version.MIK32V2: - port2_addr = PAD_CONFIG_BASE_ADDRESS + PAD_CONFIG_REGS_V2.PORT_2_CFG.value + port2_addr = mem_map.PAD_CONFIG_REGS + mem_map.PAD_CONFIG_REGS_V2.PORT_2_CFG.value else: return @@ -74,9 +47,9 @@ def gpio_init(openocd: OpenOcdTclRpc, version: MIK32_Version): def gpio_deinit(openocd: OpenOcdTclRpc, version: MIK32_Version): if version == MIK32_Version.MIK32V0: - port2_addr = PAD_CONFIG_BASE_ADDRESS + PAD_CONFIG_REGS_V0.PORT_2_CFG.value + port2_addr = mem_map.PAD_CONFIG_REGS + mem_map.PAD_CONFIG_REGS_V0.PORT_2_CFG.value elif version == MIK32_Version.MIK32V2: - port2_addr = PAD_CONFIG_BASE_ADDRESS + PAD_CONFIG_REGS_V2.PORT_2_CFG.value + port2_addr = mem_map.PAD_CONFIG_REGS + mem_map.PAD_CONFIG_REGS_V2.PORT_2_CFG.value else: return diff --git a/mik32_debug_hal/power_manager.py b/mik32_debug_hal/power_manager.py new file mode 100644 index 0000000..8c013b4 --- /dev/null +++ b/mik32_debug_hal/power_manager.py @@ -0,0 +1,33 @@ +from tclrpc import OpenOcdTclRpc +import mik32_debug_hal.registers.memory_map as mem_map +import mik32_debug_hal.registers.bitfields.power_manager as pm_fields +import mik32_debug_hal.registers.bitfields.wakeup as wake_fields + + +def pm_init(openocd: OpenOcdTclRpc): + + WU_CLOCKS_default = 128 << wake_fields.CLOCKS_BU_ADJ_RC32K_S + + AHB_default = ( + pm_fields.CLOCK_AHB_CPU_M | + pm_fields.CLOCK_AHB_EEPROM_M | + pm_fields.CLOCK_AHB_RAM_M | + pm_fields.CLOCK_AHB_SPIFI_M | + pm_fields.CLOCK_AHB_TCB_M | + pm_fields.CLOCK_AHB_DMA_M + ) + # 0x1F + APB_M_default = ( + pm_fields.CLOCK_APB_M_PM_M | + pm_fields.CLOCK_APB_M_PAD_CONFIG_M | + pm_fields.CLOCK_APB_M_WU_M + ) + # 0x89 + APB_P_default = pm_fields.CLOCK_APB_P_GPIO_2_M + # 0x00 + + openocd.halt() + openocd.write_word(mem_map.WU_CLOCKS_BU_OFFSET, WU_CLOCKS_default) + openocd.write_word(mem_map.PM_Clk_APB_P_Set_OFFSET, APB_P_default) + openocd.write_word(mem_map.PM_Clk_APB_M_Set_OFFSET, APB_M_default) + openocd.write_word(mem_map.PM_Clk_AHB_Set_OFFSET, AHB_default) diff --git a/mik32_ram.py b/mik32_debug_hal/ram.py similarity index 100% rename from mik32_ram.py rename to mik32_debug_hal/ram.py diff --git a/mik32_debug_hal/registers/bitfields/dma.py b/mik32_debug_hal/registers/bitfields/dma.py new file mode 100644 index 0000000..93f6b62 --- /dev/null +++ b/mik32_debug_hal/registers/bitfields/dma.py @@ -0,0 +1,96 @@ +# -------------------------- +# DMA register fields +# -------------------------- + +CHANNEL_COUNT = 4 + +CHANNEL_M = ((1 << CHANNEL_COUNT) - 1) + +# CONTROL + +CONTROL_CLEAR_LOCAL_IRQ_S = 0 +CONTROL_CLEAR_LOCAL_IRQ_M = ( + CHANNEL_M << CONTROL_CLEAR_LOCAL_IRQ_S) + + +def CONTROL_CLEAR_LOCAL_IRQ(i): + return ((1 << (CONTROL_CLEAR_LOCAL_IRQ_S + (i))) & CONTROL_CLEAR_LOCAL_IRQ_M) + + +CONTROL_CLEAR_GLOBAL_IRQ_S = (CHANNEL_COUNT + 0) +CONTROL_CLEAR_GLOBAL_IRQ_M = (1 << CONTROL_CLEAR_GLOBAL_IRQ_S) +CONTROL_CLEAR_ERROR_IRQ_S = (CHANNEL_COUNT + 1) +CONTROL_CLEAR_ERROR_IRQ_M = (1 << CONTROL_CLEAR_ERROR_IRQ_S) +CONTROL_GLOBAL_IRQ_ENA_S = (CHANNEL_COUNT + 2) +CONTROL_GLOBAL_IRQ_ENA_M = (1 << CONTROL_GLOBAL_IRQ_ENA_S) +CONTROL_ERROR_IRQ_ENA_S = (CHANNEL_COUNT + 3) +CONTROL_ERROR_IRQ_ENA_M = (1 << CONTROL_ERROR_IRQ_ENA_S) +CONTROL_CURRENT_VALUE_S = (CHANNEL_COUNT + 4) +CONTROL_CURRENT_VALUE_M = (1 << CONTROL_CURRENT_VALUE_S) + +CFG_CH_ENABLE_S = 0 +CFG_CH_ENABLE_M = (1 << CFG_CH_ENABLE_S) +CFG_CH_DISABLE_M = (0 << CFG_CH_ENABLE_S) + +CFG_CH_PRIOR_S = 1 +CFG_CH_PRIOR_M = (0x3 << CFG_CH_PRIOR_S) + +CFG_CH_READ_MODE_S = 3 +CFG_CH_READ_MODE_memory_M = (1 << CFG_CH_READ_MODE_S) +CFG_CH_READ_MODE_periphery_M = (0 << CFG_CH_READ_MODE_S) + +CFG_CH_WRITE_MODE_S = 4 +CFG_CH_WRITE_MODE_memory_M = (1 << CFG_CH_WRITE_MODE_S) +CFG_CH_WRITE_MODE_periphery_M = (0 << CFG_CH_WRITE_MODE_S) + +CFG_CH_READ_INCREMENT_S = 5 +CFG_CH_READ_INCREMENT_M = (1 << CFG_CH_READ_INCREMENT_S) +CFG_CH_READ_no_INCREMENT_M = (0 << CFG_CH_READ_INCREMENT_S) + +CFG_CH_READ_INCREMENT_S = 5 +CFG_CH_READ_INCREMENT_M = (1 << CFG_CH_READ_INCREMENT_S) +CFG_CH_READ_no_INCREMENT_M = (0 << CFG_CH_READ_INCREMENT_S) + +CFG_CH_WRITE_INCREMENT_S = 6 +CFG_CH_WRITE_INCREMENT_M = (1 << CFG_CH_WRITE_INCREMENT_S) +CFG_CH_WRITE_no_INCREMENT_M = (0 << CFG_CH_WRITE_INCREMENT_S) + +CFG_CH_READ_SIZE_S = 7 +CFG_CH_READ_SIZE_byte_M = (0B00 << CFG_CH_READ_SIZE_S) # байт +CFG_CH_READ_SIZE_2byte_M = (0B01 << CFG_CH_READ_SIZE_S) # полуслово +CFG_CH_READ_SIZE_4byte_M = (0B10 << CFG_CH_READ_SIZE_S) # слово +CFG_CH_READ_SIZE_rez_M = (0B11 << CFG_CH_READ_SIZE_S) # резерв + +CFG_CH_WRITE_SIZE_S = 9 +CFG_CH_WRITE_SIZE_byte_M = (0B00 << CFG_CH_WRITE_SIZE_S) # байт +CFG_CH_WRITE_SIZE_2byte_M = (0B01 << CFG_CH_WRITE_SIZE_S) # полуслово +CFG_CH_WRITE_SIZE_4byte_M = (0B10 << CFG_CH_WRITE_SIZE_S) # слово +CFG_CH_WRITE_SIZE_rez_M = (0B11 << CFG_CH_WRITE_SIZE_S) # резерв + +# Кол-во байт пакетной передачи: 2^Read_burst_size +CFG_CH_READ_BURST_SIZE_S = 11 +# Кол-во байт пакетной передачи: 2^Write_burst_size +CFG_CH_WRITE_BURST_SIZE_S = 14 + +CFG_CH_READ_REQ_S = 17 # выбор канала чтения +CFG_CH_READ_REQ_M = (0xF << CFG_CH_READ_REQ_S) + + +def CFG_CH_READ_REQ(v): + return (((v) << CFG_CH_READ_REQ_S) & CFG_CH_READ_REQ_M) + + +CFG_CH_WRITE_REQ_S = 21 # выбор канала записи +CFG_CH_WRITE_REQ_M = (0xF << CFG_CH_WRITE_REQ_S) + + +def CFG_CH_WRITE_REQ(v): + return (((v) << CFG_CH_WRITE_REQ_S) & CFG_CH_WRITE_REQ_M) + + +CFG_CH_ACK_READ_S = 25 +CFG_CH_ACK_READ_M = (1 << CFG_CH_ACK_READ_S) +CFG_CH_ACK_WRITE_S = 26 +CFG_CH_ACK_WRITE_M = (1 << CFG_CH_ACK_WRITE_S) + +STATUS_READY_S = 0 diff --git a/mik32_debug_hal/registers/bitfields/power_manager.py b/mik32_debug_hal/registers/bitfields/power_manager.py new file mode 100644 index 0000000..9b8c08e --- /dev/null +++ b/mik32_debug_hal/registers/bitfields/power_manager.py @@ -0,0 +1,77 @@ +# -------------------------- +# PM register fields +# -------------------------- + +# AHB BUS +CLOCK_AHB_CPU_S = 0 +CLOCK_AHB_CPU_M = (1 << CLOCK_AHB_CPU_S) +CLOCK_AHB_EEPROM_S = 1 +CLOCK_AHB_EEPROM_M = (1 << CLOCK_AHB_EEPROM_S) +CLOCK_AHB_RAM_S = 2 +CLOCK_AHB_RAM_M = (1 << CLOCK_AHB_RAM_S) +CLOCK_AHB_SPIFI_S = 3 +CLOCK_AHB_SPIFI_M = (1 << CLOCK_AHB_SPIFI_S) +CLOCK_AHB_TCB_S = 4 +CLOCK_AHB_TCB_M = (1 << CLOCK_AHB_TCB_S) +CLOCK_AHB_DMA_S = 5 +CLOCK_AHB_DMA_M = (1 << CLOCK_AHB_DMA_S) +CLOCK_AHB_CRYPTO_S = 6 +CLOCK_AHB_CRYPTO_M = (1 << CLOCK_AHB_CRYPTO_S) +CLOCK_AHB_CRC32_S = 7 +CLOCK_AHB_CRC32_M = (1 << CLOCK_AHB_CRC32_S) + +# APB M +CLOCK_APB_M_PM_S = 0 +CLOCK_APB_M_PM_M = (1 << CLOCK_APB_M_PM_S) +CLOCK_APB_M_EPIC_S = 1 +CLOCK_APB_M_EPIC_M = (1 << CLOCK_APB_M_EPIC_S) +CLOCK_APB_M_TIMER32_0_S = 2 +CLOCK_APB_M_TIMER32_0_M = (1 << CLOCK_APB_M_TIMER32_0_S) +CLOCK_APB_M_PAD_CONFIG_S = 3 +CLOCK_APB_M_PAD_CONFIG_M = (1 << CLOCK_APB_M_PAD_CONFIG_S) +CLOCK_APB_M_WDT_BUS_S = 4 +CLOCK_APB_M_WDT_BUS_M = (1 << CLOCK_APB_M_WDT_BUS_S) +CLOCK_APB_M_OTP_S = 5 +CLOCK_APB_M_OTP_M = (1 << CLOCK_APB_M_OTP_S) +CLOCK_APB_M_PMON_S = 6 +CLOCK_APB_M_PMON_M = (1 << CLOCK_APB_M_PMON_S) +CLOCK_APB_M_WU_S = 7 +CLOCK_APB_M_WU_M = (1 << CLOCK_APB_M_WU_S) +CLOCK_APB_M_RTC_S = 8 +CLOCK_APB_M_RTC_M = (1 << CLOCK_APB_M_RTC_S) + +# APB_P +CLOCK_APB_P_WDT_S = 0 +CLOCK_APB_P_WDT_M = (1 << CLOCK_APB_P_WDT_S) +CLOCK_APB_P_UART_0_S = 1 +CLOCK_APB_P_UART_0_M = (1 << CLOCK_APB_P_UART_0_S) +CLOCK_APB_P_UART_1_S = 2 +CLOCK_APB_P_UART_1_M = (1 << CLOCK_APB_P_UART_1_S) +CLOCK_APB_P_TIMER16_0_S = 3 +CLOCK_APB_P_TIMER16_0_M = (1 << CLOCK_APB_P_TIMER16_0_S) +CLOCK_APB_P_TIMER16_1_S = 4 +CLOCK_APB_P_TIMER16_1_M = (1 << CLOCK_APB_P_TIMER16_1_S) +CLOCK_APB_P_TIMER16_2_S = 5 +CLOCK_APB_P_TIMER16_2_M = (1 << CLOCK_APB_P_TIMER16_2_S) +CLOCK_APB_P_TIMER32_1_S = 6 +CLOCK_APB_P_TIMER32_1_M = (1 << CLOCK_APB_P_TIMER32_1_S) +CLOCK_APB_P_TIMER32_2_S = 7 +CLOCK_APB_P_TIMER32_2_M = (1 << CLOCK_APB_P_TIMER32_2_S) +CLOCK_APB_P_SPI_0_S = 8 +CLOCK_APB_P_SPI_0_M = (1 << CLOCK_APB_P_SPI_0_S) +CLOCK_APB_P_SPI_1_S = 9 +CLOCK_APB_P_SPI_1_M = (1 << CLOCK_APB_P_SPI_1_S) +CLOCK_APB_P_I2C_0_S = 10 +CLOCK_APB_P_I2C_0_M = (1 << CLOCK_APB_P_I2C_0_S) +CLOCK_APB_P_I2C_1_S = 11 +CLOCK_APB_P_I2C_1_M = (1 << CLOCK_APB_P_I2C_1_S) +CLOCK_APB_P_GPIO_0_S = 12 +CLOCK_APB_P_GPIO_0_M = (1 << CLOCK_APB_P_GPIO_0_S) +CLOCK_APB_P_GPIO_1_S = 13 +CLOCK_APB_P_GPIO_1_M = (1 << CLOCK_APB_P_GPIO_1_S) +CLOCK_APB_P_GPIO_2_S = 14 +CLOCK_APB_P_GPIO_2_M = (1 << CLOCK_APB_P_GPIO_2_S) +CLOCK_APB_P_ANALOG_S = 15 +CLOCK_APB_P_ANALOG_M = (1 << CLOCK_APB_P_ANALOG_S) +CLOCK_APB_P_GPIO_IRQ_S = 16 +CLOCK_APB_P_GPIO_IRQ_M = (1 << CLOCK_APB_P_GPIO_IRQ_S) diff --git a/mik32_debug_hal/registers/bitfields/spifi.py b/mik32_debug_hal/registers/bitfields/spifi.py new file mode 100644 index 0000000..582b895 --- /dev/null +++ b/mik32_debug_hal/registers/bitfields/spifi.py @@ -0,0 +1,111 @@ +# -------------------------- +# SPIFI register fields +# -------------------------- +# CTRL +SPIFI_CONFIG_CTRL_TIMEOUT_S = 0 +SPIFI_CONFIG_CTRL_TIMEOUT_M = (0xFFFF << SPIFI_CONFIG_CTRL_TIMEOUT_S) + + +def SPIFI_CONFIG_CTRL_TIMEOUT(v): + return (((v) << SPIFI_CONFIG_CTRL_TIMEOUT_S) & SPIFI_CONFIG_CTRL_TIMEOUT_M) + + +SPIFI_CONFIG_CTRL_CSHIGH_S = 16 +SPIFI_CONFIG_CTRL_CSHIGH_M = (0xF << SPIFI_CONFIG_CTRL_CSHIGH_S) + + +def SPIFI_CONFIG_CTRL_CSHIGH(v): + return (((v) << SPIFI_CONFIG_CTRL_CSHIGH_S) & SPIFI_CONFIG_CTRL_CSHIGH_M) + + +SPIFI_CONFIG_CTRL_CACHE_EN_S = 20 +SPIFI_CONFIG_CTRL_CACHE_EN_M = (0x1 << SPIFI_CONFIG_CTRL_CACHE_EN_S) +SPIFI_CONFIG_CTRL_D_CACHE_DIS_S = 21 +SPIFI_CONFIG_CTRL_D_CACHE_DIS_M = (0x1 << SPIFI_CONFIG_CTRL_D_CACHE_DIS_S) +SPIFI_CONFIG_CTRL_INTEN_S = 22 +SPIFI_CONFIG_CTRL_INTEN_M = (0x1 << SPIFI_CONFIG_CTRL_INTEN_S) +SPIFI_CONFIG_CTRL_MODE3_S = 23 +SPIFI_CONFIG_CTRL_MODE3_M = (0x1 << SPIFI_CONFIG_CTRL_MODE3_S) +SPIFI_CONFIG_CTRL_SCK_DIV_S = 24 +SPIFI_CONFIG_CTRL_SCK_DIV_M = (0x7 << SPIFI_CONFIG_CTRL_SCK_DIV_S) + + +def SPIFI_CONFIG_CTRL_SCK_DIV(v): + return (((v) << SPIFI_CONFIG_CTRL_SCK_DIV_S) & SPIFI_CONFIG_CTRL_SCK_DIV_M) + + +SPIFI_CONFIG_CTRL_PREFETCH_DIS_S = 27 +SPIFI_CONFIG_CTRL_PREFETCH_DIS_M = (0x1 << SPIFI_CONFIG_CTRL_PREFETCH_DIS_S) +SPIFI_CONFIG_CTRL_DUAL_S = 28 +SPIFI_CONFIG_CTRL_DUAL_M = (0x1 << SPIFI_CONFIG_CTRL_DUAL_S) +SPIFI_CONFIG_CTRL_RFCLK_S = 29 +SPIFI_CONFIG_CTRL_RFCLK_M = (0x1 << SPIFI_CONFIG_CTRL_RFCLK_S) +SPIFI_CONFIG_CTRL_FBCLK_S = 30 +SPIFI_CONFIG_CTRL_FBCLK_M = (0x1 << SPIFI_CONFIG_CTRL_FBCLK_S) +SPIFI_CONFIG_CTRL_DMAEN_S = 31 +SPIFI_CONFIG_CTRL_DMAEN_M = (0x1 << SPIFI_CONFIG_CTRL_DMAEN_S) + +# CMD +SPIFI_CONFIG_CMD_DATALEN_S = 0 +SPIFI_CONFIG_CMD_DATALEN_M = (0x3FFF << SPIFI_CONFIG_CMD_DATALEN_S) + + +def SPIFI_CONFIG_CMD_DATALEN(v): + return (((v) << SPIFI_CONFIG_CMD_DATALEN_S) & SPIFI_CONFIG_CMD_DATALEN_M) + + +SPIFI_CONFIG_CMD_POLL_S = 14 +SPIFI_CONFIG_CMD_POLL_M = (0x1 << SPIFI_CONFIG_CMD_POLL_S) +SPIFI_CONFIG_CMD_DOUT_S = 15 +SPIFI_CONFIG_CMD_DOUT_M = (0x1 << SPIFI_CONFIG_CMD_DOUT_S) +SPIFI_CONFIG_CMD_INTLEN_S = 16 +SPIFI_CONFIG_CMD_INTLEN_M = (0x7 << SPIFI_CONFIG_CMD_INTLEN_S) +SPIFI_CONFIG_CMD_FIELDFORM_S = 19 +SPIFI_CONFIG_CMD_FIELDFORM_M = (0x3 << SPIFI_CONFIG_CMD_FIELDFORM_S) +SPIFI_CONFIG_CMD_FRAMEFORM_S = 21 +SPIFI_CONFIG_CMD_FRAMEFORM_M = (0x7 << SPIFI_CONFIG_CMD_FRAMEFORM_S) +SPIFI_CONFIG_CMD_OPCODE_S = 24 +SPIFI_CONFIG_CMD_OPCODE_M = (0xFF << SPIFI_CONFIG_CMD_OPCODE_S) + +SPIFI_CONFIG_CMD_DATALEN_BUSY_INDEX_S = 0 +SPIFI_CONFIG_CMD_DATALEN_BUSY_DONE_VALUE_S = 3 + +SPIFI_CONFIG_CMD_FRAMEFORM_RESERVED = 0 +SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_NOADDR = 1 +SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_1ADDR = 2 +SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_2ADDR = 3 +SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR = 4 +SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_4ADDR = 5 +SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_3ADDR = 6 +SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_4ADDR = 7 + +SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL = 0 +SPIFI_CONFIG_CMD_FIELDFORM_DATA_PARALLEL = 1 +SPIFI_CONFIG_CMD_FIELDFORM_OPCODE_SERIAL = 2 +SPIFI_CONFIG_CMD_FIELDFORM_ALL_PARALLEL = 3 + +# MCMD +SPIFI_CONFIG_MCMD_POLL_S = 14 +SPIFI_CONFIG_MCMD_POLL_M = (0x1 << SPIFI_CONFIG_MCMD_POLL_S) +SPIFI_CONFIG_MCMD_DOUT_S = 15 +SPIFI_CONFIG_MCMD_DOUT_M = (0x1 << SPIFI_CONFIG_MCMD_DOUT_S) +SPIFI_CONFIG_MCMD_INTLEN_S = 16 +SPIFI_CONFIG_MCMD_INTLEN_M = (0x7 << SPIFI_CONFIG_MCMD_INTLEN_S) +SPIFI_CONFIG_MCMD_FIELDFORM_S = 19 +SPIFI_CONFIG_MCMD_FIELDFORM_M = (0x3 << SPIFI_CONFIG_MCMD_FIELDFORM_S) +SPIFI_CONFIG_MCMD_FRAMEFORM_S = 21 +SPIFI_CONFIG_MCMD_FRAMEFORM_M = (0x7 << SPIFI_CONFIG_MCMD_FRAMEFORM_S) +SPIFI_CONFIG_MCMD_OPCODE_S = 24 +SPIFI_CONFIG_MCMD_OPCODE_M = (0xFF << SPIFI_CONFIG_MCMD_OPCODE_S) + +# STATUS +SPIFI_CONFIG_STAT_MCINIT_S = 0 +SPIFI_CONFIG_STAT_MCINIT_M = (0x1 << SPIFI_CONFIG_STAT_MCINIT_S) +SPIFI_CONFIG_STAT_CMD_S = 1 +SPIFI_CONFIG_STAT_CMD_M = (0x1 << SPIFI_CONFIG_STAT_CMD_S) +SPIFI_CONFIG_STAT_RESET_S = 4 +SPIFI_CONFIG_STAT_RESET_M = (0x1 << SPIFI_CONFIG_STAT_RESET_S) +SPIFI_CONFIG_STAT_INTRQ_S = 5 +SPIFI_CONFIG_STAT_INTRQ_M = (0x1 << SPIFI_CONFIG_STAT_INTRQ_S) +SPIFI_CONFIG_STAT_VERSION_S = 24 +SPIFI_CONFIG_STAT_VERSION_M = (0xFF << SPIFI_CONFIG_STAT_VERSION_S) \ No newline at end of file diff --git a/mik32_debug_hal/registers/bitfields/wakeup.py b/mik32_debug_hal/registers/bitfields/wakeup.py new file mode 100644 index 0000000..75ae964 --- /dev/null +++ b/mik32_debug_hal/registers/bitfields/wakeup.py @@ -0,0 +1,15 @@ +# -------------------------- +# WU register fields +# -------------------------- + +# CLOCKS_BU +CLOCKS_BU_OCS32K_EN_S = 0 +CLOCKS_BU_OCS32K_EN_M = (1 << CLOCKS_BU_OCS32K_EN_S) +CLOCKS_BU_RC32K_EN_S = 1 +CLOCKS_BU_RC32K_EN_M = (1 << CLOCKS_BU_RC32K_EN_S) +CLOCKS_BU_ADJ_RC32K_S = 2 +CLOCKS_BU_ADJ_RC32K_M = (0b11111111 << CLOCKS_BU_ADJ_RC32K_S) +CLOCKS_BU_RTC_CLK_MUX_S = 10 +CLOCKS_BU_RTC_CLK_MUX_M = (1 << CLOCKS_BU_RTC_CLK_MUX_S) +CLOCKS_BU_OSC32K_SM_S = 14 +CLOCKS_BU_OSC32K_SM_M = (1 << CLOCKS_BU_OSC32K_SM_S) diff --git a/mik32_debug_hal/registers/memory_map.py b/mik32_debug_hal/registers/memory_map.py new file mode 100644 index 0000000..4bab332 --- /dev/null +++ b/mik32_debug_hal/registers/memory_map.py @@ -0,0 +1,89 @@ +# -------------------------- +# DMA register offset +# -------------------------- +from enum import Enum + + +DMA_REGS = 0x00040000 +DMA_CONTROL = DMA_REGS + 0x40 + +DMA_CHANNEL_SIZEOF = 0x4 * 4 + + +def DMA_CHANNEL_DESTINATION(i): + return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*0 + + +def DMA_CHANNEL_SOURCE(i): + return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*1 + + +def DMA_CHANNEL_LEN(i): + return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*2 + + +def DMA_CHANNEL_CONFIG(i): + return DMA_REGS + i*DMA_CHANNEL_SIZEOF + 0x4*3 + + +# -------------------------- +# SPIFI register offset +# -------------------------- +SPIFI_REGS = 0x00070000 + +SPIFI_CONFIG_CTRL = SPIFI_REGS + 0x000 +SPIFI_CONFIG_CMD = SPIFI_REGS + 0x004 +SPIFI_CONFIG_ADDR = SPIFI_REGS + 0x008 +SPIFI_CONFIG_IDATA = SPIFI_REGS + 0x00C +SPIFI_CONFIG_CLIMIT = SPIFI_REGS + 0x010 +SPIFI_CONFIG_DATA32 = SPIFI_REGS + 0x014 +SPIFI_CONFIG_MCMD = SPIFI_REGS + 0x018 +SPIFI_CONFIG_STAT = SPIFI_REGS + 0x01C + + +# -------------------------- +# PM register offset +# -------------------------- + + +PM_REGS = 0x000050000 + +PM_Clk_AHB_Set_OFFSET = PM_REGS + 0x0C +PM_Clk_APB_M_Set_OFFSET = PM_REGS + 0x14 +PM_Clk_APB_P_Set_OFFSET = PM_REGS + 0x1C + + +# -------------------------- +# WU register offset +# -------------------------- +WU_REGS = 0x00060000 + +WU_CLOCKS_BU_OFFSET = WU_REGS + 0x10 + + +# -------------------------- +# GPIO register offset +# -------------------------- +PAD_CONFIG_REGS = 0x00050C00 + +class PAD_CONFIG_REGS_V0(Enum): + PORT_0_CFG = 0x00 + PORT_1_CFG = 0x04 + PORT_2_CFG = 0x08 + PORT_0_DS = 0x0C + PORT_1_DS = 0x10 + PORT_2_DS = 0x14 + PORT_0_PUD = 0x18 + PORT_1_PUD = 0x1C + PORT_2_PUD = 0x20 + +class PAD_CONFIG_REGS_V2(Enum): + PORT_0_CFG = 0x00 + PORT_0_DS = 0x04 + PORT_0_PUD = 0x08 + PORT_1_CFG = 0x0C + PORT_1_DS = 0x10 + PORT_1_PUD = 0x14 + PORT_2_CFG = 0x18 + PORT_2_DS = 0x1C + PORT_2_PUD = 0x20 diff --git a/mik32_spifi.py b/mik32_debug_hal/spifi.py similarity index 77% rename from mik32_spifi.py rename to mik32_debug_hal/spifi.py index d84445d..49a47bf 100644 --- a/mik32_spifi.py +++ b/mik32_debug_hal/spifi.py @@ -6,134 +6,9 @@ from typing import Dict, List, Union import time from tclrpc import TclException from tclrpc import OpenOcdTclRpc -from mik32_dma import DMA, ChannelMode, ChannelIndex, ChannelAck, ChannelIncrement, ChannelPriority, ChannelRequest, ChannelSize - - -# -------------------------- -# SPIFI register offset -# -------------------------- -SPIFI_REGS_BASE_ADDRESS = 0x00070000 - -SPIFI_CONFIG_CTRL = SPIFI_REGS_BASE_ADDRESS + 0x000 -SPIFI_CONFIG_CMD = SPIFI_REGS_BASE_ADDRESS + 0x004 -SPIFI_CONFIG_ADDR = SPIFI_REGS_BASE_ADDRESS + 0x008 -SPIFI_CONFIG_IDATA = SPIFI_REGS_BASE_ADDRESS + 0x00C -SPIFI_CONFIG_CLIMIT = SPIFI_REGS_BASE_ADDRESS + 0x010 -SPIFI_CONFIG_DATA32 = SPIFI_REGS_BASE_ADDRESS + 0x014 -SPIFI_CONFIG_MCMD = SPIFI_REGS_BASE_ADDRESS + 0x018 -SPIFI_CONFIG_STAT = SPIFI_REGS_BASE_ADDRESS + 0x01C - -# -------------------------- -# SPIFI register fields -# -------------------------- -# CTRL -SPIFI_CONFIG_CTRL_TIMEOUT_S = 0 -SPIFI_CONFIG_CTRL_TIMEOUT_M = (0xFFFF << SPIFI_CONFIG_CTRL_TIMEOUT_S) - - -def SPIFI_CONFIG_CTRL_TIMEOUT(v): - return (((v) << SPIFI_CONFIG_CTRL_TIMEOUT_S) & SPIFI_CONFIG_CTRL_TIMEOUT_M) - - -SPIFI_CONFIG_CTRL_CSHIGH_S = 16 -SPIFI_CONFIG_CTRL_CSHIGH_M = (0xF << SPIFI_CONFIG_CTRL_CSHIGH_S) - - -def SPIFI_CONFIG_CTRL_CSHIGH(v): - return (((v) << SPIFI_CONFIG_CTRL_CSHIGH_S) & SPIFI_CONFIG_CTRL_CSHIGH_M) - - -SPIFI_CONFIG_CTRL_CACHE_EN_S = 20 -SPIFI_CONFIG_CTRL_CACHE_EN_M = (0x1 << SPIFI_CONFIG_CTRL_CACHE_EN_S) -SPIFI_CONFIG_CTRL_D_CACHE_DIS_S = 21 -SPIFI_CONFIG_CTRL_D_CACHE_DIS_M = (0x1 << SPIFI_CONFIG_CTRL_D_CACHE_DIS_S) -SPIFI_CONFIG_CTRL_INTEN_S = 22 -SPIFI_CONFIG_CTRL_INTEN_M = (0x1 << SPIFI_CONFIG_CTRL_INTEN_S) -SPIFI_CONFIG_CTRL_MODE3_S = 23 -SPIFI_CONFIG_CTRL_MODE3_M = (0x1 << SPIFI_CONFIG_CTRL_MODE3_S) -SPIFI_CONFIG_CTRL_SCK_DIV_S = 24 -SPIFI_CONFIG_CTRL_SCK_DIV_M = (0x7 << SPIFI_CONFIG_CTRL_SCK_DIV_S) - - -def SPIFI_CONFIG_CTRL_SCK_DIV(v): - return (((v) << SPIFI_CONFIG_CTRL_SCK_DIV_S) & SPIFI_CONFIG_CTRL_SCK_DIV_M) - - -SPIFI_CONFIG_CTRL_PREFETCH_DIS_S = 27 -SPIFI_CONFIG_CTRL_PREFETCH_DIS_M = (0x1 << SPIFI_CONFIG_CTRL_PREFETCH_DIS_S) -SPIFI_CONFIG_CTRL_DUAL_S = 28 -SPIFI_CONFIG_CTRL_DUAL_M = (0x1 << SPIFI_CONFIG_CTRL_DUAL_S) -SPIFI_CONFIG_CTRL_RFCLK_S = 29 -SPIFI_CONFIG_CTRL_RFCLK_M = (0x1 << SPIFI_CONFIG_CTRL_RFCLK_S) -SPIFI_CONFIG_CTRL_FBCLK_S = 30 -SPIFI_CONFIG_CTRL_FBCLK_M = (0x1 << SPIFI_CONFIG_CTRL_FBCLK_S) -SPIFI_CONFIG_CTRL_DMAEN_S = 31 -SPIFI_CONFIG_CTRL_DMAEN_M = (0x1 << SPIFI_CONFIG_CTRL_DMAEN_S) - -# CMD -SPIFI_CONFIG_CMD_DATALEN_S = 0 -SPIFI_CONFIG_CMD_DATALEN_M = (0x3FFF << SPIFI_CONFIG_CMD_DATALEN_S) - - -def SPIFI_CONFIG_CMD_DATALEN(v): - return (((v) << SPIFI_CONFIG_CMD_DATALEN_S) & SPIFI_CONFIG_CMD_DATALEN_M) - - -SPIFI_CONFIG_CMD_POLL_S = 14 -SPIFI_CONFIG_CMD_POLL_M = (0x1 << SPIFI_CONFIG_CMD_POLL_S) -SPIFI_CONFIG_CMD_DOUT_S = 15 -SPIFI_CONFIG_CMD_DOUT_M = (0x1 << SPIFI_CONFIG_CMD_DOUT_S) -SPIFI_CONFIG_CMD_INTLEN_S = 16 -SPIFI_CONFIG_CMD_INTLEN_M = (0x7 << SPIFI_CONFIG_CMD_INTLEN_S) -SPIFI_CONFIG_CMD_FIELDFORM_S = 19 -SPIFI_CONFIG_CMD_FIELDFORM_M = (0x3 << SPIFI_CONFIG_CMD_FIELDFORM_S) -SPIFI_CONFIG_CMD_FRAMEFORM_S = 21 -SPIFI_CONFIG_CMD_FRAMEFORM_M = (0x7 << SPIFI_CONFIG_CMD_FRAMEFORM_S) -SPIFI_CONFIG_CMD_OPCODE_S = 24 -SPIFI_CONFIG_CMD_OPCODE_M = (0xFF << SPIFI_CONFIG_CMD_OPCODE_S) - -SPIFI_CONFIG_CMD_DATALEN_BUSY_INDEX_S = 0 -SPIFI_CONFIG_CMD_DATALEN_BUSY_DONE_VALUE_S = 3 - -SPIFI_CONFIG_CMD_FRAMEFORM_RESERVED = 0 -SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_NOADDR = 1 -SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_1ADDR = 2 -SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_2ADDR = 3 -SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR = 4 -SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_4ADDR = 5 -SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_3ADDR = 6 -SPIFI_CONFIG_CMD_FRAMEFORM_NOOPCODE_4ADDR = 7 - -SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL = 0 -SPIFI_CONFIG_CMD_FIELDFORM_DATA_PARALLEL = 1 -SPIFI_CONFIG_CMD_FIELDFORM_OPCODE_SERIAL = 2 -SPIFI_CONFIG_CMD_FIELDFORM_ALL_PARALLEL = 3 - -# MCMD -SPIFI_CONFIG_MCMD_POLL_S = 14 -SPIFI_CONFIG_MCMD_POLL_M = (0x1 << SPIFI_CONFIG_MCMD_POLL_S) -SPIFI_CONFIG_MCMD_DOUT_S = 15 -SPIFI_CONFIG_MCMD_DOUT_M = (0x1 << SPIFI_CONFIG_MCMD_DOUT_S) -SPIFI_CONFIG_MCMD_INTLEN_S = 16 -SPIFI_CONFIG_MCMD_INTLEN_M = (0x7 << SPIFI_CONFIG_MCMD_INTLEN_S) -SPIFI_CONFIG_MCMD_FIELDFORM_S = 19 -SPIFI_CONFIG_MCMD_FIELDFORM_M = (0x3 << SPIFI_CONFIG_MCMD_FIELDFORM_S) -SPIFI_CONFIG_MCMD_FRAMEFORM_S = 21 -SPIFI_CONFIG_MCMD_FRAMEFORM_M = (0x7 << SPIFI_CONFIG_MCMD_FRAMEFORM_S) -SPIFI_CONFIG_MCMD_OPCODE_S = 24 -SPIFI_CONFIG_MCMD_OPCODE_M = (0xFF << SPIFI_CONFIG_MCMD_OPCODE_S) - -# STATUS -SPIFI_CONFIG_STAT_MCINIT_S = 0 -SPIFI_CONFIG_STAT_MCINIT_M = (0x1 << SPIFI_CONFIG_STAT_MCINIT_S) -SPIFI_CONFIG_STAT_CMD_S = 1 -SPIFI_CONFIG_STAT_CMD_M = (0x1 << SPIFI_CONFIG_STAT_CMD_S) -SPIFI_CONFIG_STAT_RESET_S = 4 -SPIFI_CONFIG_STAT_RESET_M = (0x1 << SPIFI_CONFIG_STAT_RESET_S) -SPIFI_CONFIG_STAT_INTRQ_S = 5 -SPIFI_CONFIG_STAT_INTRQ_M = (0x1 << SPIFI_CONFIG_STAT_INTRQ_S) -SPIFI_CONFIG_STAT_VERSION_S = 24 -SPIFI_CONFIG_STAT_VERSION_M = (0xFF << SPIFI_CONFIG_STAT_VERSION_S) +from mik32_debug_hal.dma import DMA, ChannelMode, ChannelIndex, ChannelAck, ChannelIncrement, ChannelPriority, ChannelRequest, ChannelSize +import mik32_debug_hal.registers.memory_map as mem_map +import mik32_debug_hal.registers.bitfields.spifi as spifi_fields # -------------------------- # Commands @@ -182,22 +57,22 @@ class SREG_Num(Enum): def spifi_intrq_clear(openocd: OpenOcdTclRpc): - openocd.write_word(SPIFI_CONFIG_STAT, openocd.read_word(SPIFI_CONFIG_STAT) | - SPIFI_CONFIG_STAT_INTRQ_M) + openocd.write_word(mem_map.SPIFI_CONFIG_STAT, openocd.read_word(mem_map.SPIFI_CONFIG_STAT) | + spifi_fields.SPIFI_CONFIG_STAT_INTRQ_M) INIT_DELAY = 0.001 def spifi_init_periphery(openocd: OpenOcdTclRpc): - openocd.write_word(SPIFI_CONFIG_STAT, openocd.read_word(SPIFI_CONFIG_STAT) | + openocd.write_word(mem_map.SPIFI_CONFIG_STAT, openocd.read_word(mem_map.SPIFI_CONFIG_STAT) | # SPIFI_CONFIG_STAT_INTRQ_M | - SPIFI_CONFIG_STAT_RESET_M) + spifi_fields.SPIFI_CONFIG_STAT_RESET_M) # openocd.write_word(SPIFI_CONFIG_CTRL, openocd.read_word( # SPIFI_CONFIG_CTRL) | (7 << SPIFI_CONFIG_CTRL_SCK_DIV_S)) - openocd.write_word(SPIFI_CONFIG_ADDR, 0x00) - openocd.write_word(SPIFI_CONFIG_IDATA, 0x00) - openocd.write_word(SPIFI_CONFIG_CLIMIT, 0x00) + openocd.write_word(mem_map.SPIFI_CONFIG_ADDR, 0x00) + openocd.write_word(mem_map.SPIFI_CONFIG_IDATA, 0x00) + openocd.write_word(mem_map.SPIFI_CONFIG_CLIMIT, 0x00) time.sleep(INIT_DELAY) @@ -207,26 +82,26 @@ def spifi_init(openocd: OpenOcdTclRpc): spifi_init_periphery(openocd) - control = openocd.read_word(SPIFI_CONFIG_CTRL) - control |= SPIFI_CONFIG_CTRL_DMAEN_M - openocd.write_word(SPIFI_CONFIG_CTRL, control) + control = openocd.read_word(mem_map.SPIFI_CONFIG_CTRL) + control |= spifi_fields.SPIFI_CONFIG_CTRL_DMAEN_M + openocd.write_word(mem_map.SPIFI_CONFIG_CTRL, control) time.sleep(INIT_DELAY) def spifi_init_memory(openocd: OpenOcdTclRpc): - openocd.write_word(SPIFI_CONFIG_STAT, openocd.read_word(SPIFI_CONFIG_STAT) | - SPIFI_CONFIG_STAT_INTRQ_M | - SPIFI_CONFIG_STAT_RESET_M) + openocd.write_word(mem_map.SPIFI_CONFIG_STAT, openocd.read_word(mem_map.SPIFI_CONFIG_STAT) | + spifi_fields.SPIFI_CONFIG_STAT_INTRQ_M | + spifi_fields.SPIFI_CONFIG_STAT_RESET_M) # openocd.write_word(SPIFI_CONFIG_CTRL, openocd.read_word( # SPIFI_CONFIG_CTRL) | (7 << SPIFI_CONFIG_CTRL_SCK_DIV_S)) - openocd.write_word(SPIFI_CONFIG_ADDR, 0x00) - openocd.write_word(SPIFI_CONFIG_IDATA, 0x00) - openocd.write_word(SPIFI_CONFIG_CLIMIT, 0x00) - openocd.write_word(SPIFI_CONFIG_MCMD, (0 << SPIFI_CONFIG_MCMD_INTLEN_S) | - (SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL << SPIFI_CONFIG_MCMD_FIELDFORM_S) | - (SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR << SPIFI_CONFIG_MCMD_FRAMEFORM_S) | - (READ_DATA_COMMAND << SPIFI_CONFIG_MCMD_OPCODE_S)) + openocd.write_word(mem_map.SPIFI_CONFIG_ADDR, 0x00) + openocd.write_word(mem_map.SPIFI_CONFIG_IDATA, 0x00) + openocd.write_word(mem_map.SPIFI_CONFIG_CLIMIT, 0x00) + openocd.write_word(mem_map.SPIFI_CONFIG_MCMD, (0 << spifi_fields.SPIFI_CONFIG_MCMD_INTLEN_S) | + (spifi_fields.SPIFI_CONFIG_CMD_FIELDFORM_ALL_SERIAL << spifi_fields.SPIFI_CONFIG_MCMD_FIELDFORM_S) | + (spifi_fields.SPIFI_CONFIG_CMD_FRAMEFORM_OPCODE_3ADDR << spifi_fields.SPIFI_CONFIG_MCMD_FRAMEFORM_S) | + (READ_DATA_COMMAND << spifi_fields.SPIFI_CONFIG_MCMD_OPCODE_S)) time.sleep(INIT_DELAY) @@ -235,7 +110,7 @@ def SPIFI_WaitIntrqTimeout(openocd: OpenOcdTclRpc, timeout: int) -> int: timeout_inner = timeout while timeout_inner: timeout_inner -= 1 - if (openocd.read_word(SPIFI_CONFIG_STAT) & SPIFI_CONFIG_STAT_INTRQ_M) != 0: + if (openocd.read_word(mem_map.SPIFI_CONFIG_STAT) & spifi_fields.SPIFI_CONFIG_STAT_INTRQ_M) != 0: return 1 return 0 @@ -288,17 +163,17 @@ def spifi_send_command( dma.channels[0].start( 0x02003F00, - SPIFI_CONFIG_DATA32, + mem_map.SPIFI_CONFIG_DATA32, 255 ) elif (dma is not None) and (direction == SPIFI_Direction.READ): dma.channels[1].start( - SPIFI_CONFIG_DATA32, + mem_map.SPIFI_CONFIG_DATA32, 0x02003F00, 255 ) - openocd.write_memory(SPIFI_CONFIG_ADDR, 32, [address, idata]) + openocd.write_memory(mem_map.SPIFI_CONFIG_ADDR, 32, [address, idata]) # # spifi_intrq_clear(openocd) # openocd.write_word(SPIFI_CONFIG_CMD, (cmd << SPIFI_CONFIG_CMD_OPCODE_S) | @@ -309,14 +184,14 @@ def spifi_send_command( # (direction.value << SPIFI_CONFIG_CMD_DOUT_S)) # # spifi_wait_intrq_timeout(openocd, "Timeout executing write enable command") - cmd_write_value = ((cmd << SPIFI_CONFIG_CMD_OPCODE_S) | - (frameform.value << SPIFI_CONFIG_CMD_FRAMEFORM_S) | - (fieldform.value << SPIFI_CONFIG_CMD_FIELDFORM_S) | - (byte_count << SPIFI_CONFIG_CMD_DATALEN_S) | - (idata_length << SPIFI_CONFIG_CMD_INTLEN_S) | - (direction.value << SPIFI_CONFIG_CMD_DOUT_S)) + cmd_write_value = ((cmd << spifi_fields.SPIFI_CONFIG_CMD_OPCODE_S) | + (frameform.value << spifi_fields.SPIFI_CONFIG_CMD_FRAMEFORM_S) | + (fieldform.value << spifi_fields.SPIFI_CONFIG_CMD_FIELDFORM_S) | + (byte_count << spifi_fields.SPIFI_CONFIG_CMD_DATALEN_S) | + (idata_length << spifi_fields.SPIFI_CONFIG_CMD_INTLEN_S) | + (direction.value << spifi_fields.SPIFI_CONFIG_CMD_DOUT_S)) - openocd.write_memory(SPIFI_CONFIG_CMD, 32, [cmd_write_value]) + openocd.write_memory(mem_map.SPIFI_CONFIG_CMD, 32, [cmd_write_value]) if direction == SPIFI_Direction.READ: out_list = [] @@ -327,7 +202,7 @@ def spifi_send_command( return out_list else: for i in range(byte_count): - out_list.append(openocd.read_memory(SPIFI_CONFIG_DATA32, 8, 1)[0]) + out_list.append(openocd.read_memory(mem_map.SPIFI_CONFIG_DATA32, 8, 1)[0]) return out_list if direction == SPIFI_Direction.WRITE: @@ -336,11 +211,11 @@ def spifi_send_command( else: if (byte_count % 4) == 0: for i in range(0, byte_count, 4): - openocd.write_memory(SPIFI_CONFIG_DATA32, 32, [ + openocd.write_memory(mem_map.SPIFI_CONFIG_DATA32, 32, [ data[i] + data[i+1] * 256 + data[i+2] * 256 * 256 + data[i+3] * 256 * 256 * 256]) else: for i in range(byte_count): - openocd.write_memory(SPIFI_CONFIG_DATA32, 8, [data[i]]) + openocd.write_memory(mem_map.SPIFI_CONFIG_DATA32, 8, [data[i]]) return [] diff --git a/mik32_dma.py b/mik32_dma.py deleted file mode 100644 index 9ac5a34..0000000 --- a/mik32_dma.py +++ /dev/null @@ -1,326 +0,0 @@ -from enum import Enum -from typing import Dict, List -import time -from tclrpc import TclException -from tclrpc import OpenOcdTclRpc - - -# -------------------------- -# DMA register offset -# -------------------------- -DMA_REGS_BASE_ADDRESS = 0x00040000 - -DMA_CONTROL = DMA_REGS_BASE_ADDRESS + 0x40 - -DMA_CHANNEL_SIZEOF = 0x4 * 4 - - -def DMA_CHANNEL_DESTINATION(i): - return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*0 - - -def DMA_CHANNEL_SOURCE(i): - return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*1 - - -def DMA_CHANNEL_LEN(i): - return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*2 - - -def DMA_CHANNEL_CONFIG(i): - return DMA_REGS_BASE_ADDRESS + i*DMA_CHANNEL_SIZEOF + 0x4*3 - -# -------------------------- -# DMA register fields -# -------------------------- - - -DMA_CHANNEL_COUNT = 4 - -DMA_CHANNEL_M = ((1 << DMA_CHANNEL_COUNT) - 1) - -# DMA_CONTROL - -DMA_CONTROL_CLEAR_LOCAL_IRQ_S = 0 -DMA_CONTROL_CLEAR_LOCAL_IRQ_M = ( - DMA_CHANNEL_M << DMA_CONTROL_CLEAR_LOCAL_IRQ_S) - - -def DMA_CONTROL_CLEAR_LOCAL_IRQ(i): - return ((1 << (DMA_CONTROL_CLEAR_LOCAL_IRQ_S + (i))) & DMA_CONTROL_CLEAR_LOCAL_IRQ_M) - - -DMA_CONTROL_CLEAR_GLOBAL_IRQ_S = (DMA_CHANNEL_COUNT + 0) -DMA_CONTROL_CLEAR_GLOBAL_IRQ_M = (1 << DMA_CONTROL_CLEAR_GLOBAL_IRQ_S) -DMA_CONTROL_CLEAR_ERROR_IRQ_S = (DMA_CHANNEL_COUNT + 1) -DMA_CONTROL_CLEAR_ERROR_IRQ_M = (1 << DMA_CONTROL_CLEAR_ERROR_IRQ_S) -DMA_CONTROL_GLOBAL_IRQ_ENA_S = (DMA_CHANNEL_COUNT + 2) -DMA_CONTROL_GLOBAL_IRQ_ENA_M = (1 << DMA_CONTROL_GLOBAL_IRQ_ENA_S) -DMA_CONTROL_ERROR_IRQ_ENA_S = (DMA_CHANNEL_COUNT + 3) -DMA_CONTROL_ERROR_IRQ_ENA_M = (1 << DMA_CONTROL_ERROR_IRQ_ENA_S) -DMA_CONTROL_CURRENT_VALUE_S = (DMA_CHANNEL_COUNT + 4) -DMA_CONTROL_CURRENT_VALUE_M = (1 << DMA_CONTROL_CURRENT_VALUE_S) - -DMA_CFG_CH_ENABLE_S = 0 -DMA_CFG_CH_ENABLE_M = (1 << DMA_CFG_CH_ENABLE_S) -DMA_CFG_CH_DISABLE_M = (0 << DMA_CFG_CH_ENABLE_S) - -DMA_CFG_CH_PRIOR_S = 1 -DMA_CFG_CH_PRIOR_M = (0x3 << DMA_CFG_CH_PRIOR_S) - -DMA_CFG_CH_READ_MODE_S = 3 -DMA_CFG_CH_READ_MODE_memory_M = (1 << DMA_CFG_CH_READ_MODE_S) -DMA_CFG_CH_READ_MODE_periphery_M = (0 << DMA_CFG_CH_READ_MODE_S) - -DMA_CFG_CH_WRITE_MODE_S = 4 -DMA_CFG_CH_WRITE_MODE_memory_M = (1 << DMA_CFG_CH_WRITE_MODE_S) -DMA_CFG_CH_WRITE_MODE_periphery_M = (0 << DMA_CFG_CH_WRITE_MODE_S) - -DMA_CFG_CH_READ_INCREMENT_S = 5 -DMA_CFG_CH_READ_INCREMENT_M = (1 << DMA_CFG_CH_READ_INCREMENT_S) -DMA_CFG_CH_READ_no_INCREMENT_M = (0 << DMA_CFG_CH_READ_INCREMENT_S) - -DMA_CFG_CH_READ_INCREMENT_S = 5 -DMA_CFG_CH_READ_INCREMENT_M = (1 << DMA_CFG_CH_READ_INCREMENT_S) -DMA_CFG_CH_READ_no_INCREMENT_M = (0 << DMA_CFG_CH_READ_INCREMENT_S) - -DMA_CFG_CH_WRITE_INCREMENT_S = 6 -DMA_CFG_CH_WRITE_INCREMENT_M = (1 << DMA_CFG_CH_WRITE_INCREMENT_S) -DMA_CFG_CH_WRITE_no_INCREMENT_M = (0 << DMA_CFG_CH_WRITE_INCREMENT_S) - -DMA_CFG_CH_READ_SIZE_S = 7 -DMA_CFG_CH_READ_SIZE_byte_M = (0B00 << DMA_CFG_CH_READ_SIZE_S) # байт -DMA_CFG_CH_READ_SIZE_2byte_M = (0B01 << DMA_CFG_CH_READ_SIZE_S) # полуслово -DMA_CFG_CH_READ_SIZE_4byte_M = (0B10 << DMA_CFG_CH_READ_SIZE_S) # слово -DMA_CFG_CH_READ_SIZE_rez_M = (0B11 << DMA_CFG_CH_READ_SIZE_S) # резерв - -DMA_CFG_CH_WRITE_SIZE_S = 9 -DMA_CFG_CH_WRITE_SIZE_byte_M = (0B00 << DMA_CFG_CH_WRITE_SIZE_S) # байт -DMA_CFG_CH_WRITE_SIZE_2byte_M = (0B01 << DMA_CFG_CH_WRITE_SIZE_S) # полуслово -DMA_CFG_CH_WRITE_SIZE_4byte_M = (0B10 << DMA_CFG_CH_WRITE_SIZE_S) # слово -DMA_CFG_CH_WRITE_SIZE_rez_M = (0B11 << DMA_CFG_CH_WRITE_SIZE_S) # резерв - -# Кол-во байт пакетной передачи: 2^Read_burst_size -DMA_CFG_CH_READ_BURST_SIZE_S = 11 -# Кол-во байт пакетной передачи: 2^Write_burst_size -DMA_CFG_CH_WRITE_BURST_SIZE_S = 14 - -DMA_CFG_CH_READ_REQ_S = 17 # выбор канала чтения -DMA_CFG_CH_READ_REQ_M = (0xF << DMA_CFG_CH_READ_REQ_S) - - -def DMA_CFG_CH_READ_REQ(v): - return (((v) << DMA_CFG_CH_READ_REQ_S) & DMA_CFG_CH_READ_REQ_M) - - -DMA_CFG_CH_WRITE_REQ_S = 21 # выбор канала записи -DMA_CFG_CH_WRITE_REQ_M = (0xF << DMA_CFG_CH_WRITE_REQ_S) - - -def DMA_CFG_CH_WRITE_REQ(v): - return (((v) << DMA_CFG_CH_WRITE_REQ_S) & DMA_CFG_CH_WRITE_REQ_M) - - -DMA_CFG_CH_ACK_READ_S = 25 -DMA_CFG_CH_ACK_READ_M = (1 << DMA_CFG_CH_ACK_READ_S) -DMA_CFG_CH_ACK_WRITE_S = 26 -DMA_CFG_CH_ACK_WRITE_M = (1 << DMA_CFG_CH_ACK_WRITE_S) - -DMA_STATUS_READY_S = 0 - - -# ReadStatus. Разрешить читать текущий статус канала -class CurrentValue(Enum): - ENABLE = 0 # Текущие значения - DISABLE = 1 # Значения при настройке - - -class ChannelIndex(Enum): - CHANNEL_0 = 0 - CHANNEL_1 = 1 - CHANNEL_2 = 2 - CHANNEL_3 = 3 - - -class ChannelPriority(Enum): - LOW = 0 - MEDIUM = 1 - HIGH = 2 - VERY_HIGH = 3 - - -class ChannelMode(Enum): - PERIPHERY = 0 - MEMORY = 1 - - -class ChannelIncrement(Enum): - DISABLE = 0 - ENABLE = 1 - - -class ChannelSize(Enum): - BYTE = 0 - HALFWORD = 1 - WORD = 1 - - -class ChannelAck(Enum): - DISABLE = 0 - ENABLE = 1 - - -class ChannelRequest(Enum): - USART_0_REQUEST = 0 - USART_1_REQUEST = 1 - CRYPTO_REQUEST = 2 - SPI_0_REQUEST = 3 - SPI_1_REQUEST = 4 - I2C_0_REQUEST = 5 - I2C_1_REQUEST = 6 - SPIFI_REQUEST = 7 - TIMER32_1_REQUEST = 8 - TIMER32_2_REQUEST = 9 - TIMER32_0_REQUEST = 10 - - -class DMA_Channel: - openocd: OpenOcdTclRpc - - write_buffer: int = 0 - - channel: ChannelIndex - priority: ChannelPriority - - read_mode: ChannelMode - read_increment: ChannelIncrement - read_size: ChannelSize - read_ack: ChannelAck - read_burst_size: int - read_request: ChannelRequest - - write_mode: ChannelMode - write_increment: ChannelIncrement - write_size: ChannelSize - write_ack: ChannelAck - write_burst_size: int - write_request: ChannelRequest - - def __init__(self, openocd: OpenOcdTclRpc): - self.openocd = openocd - - def set_source(self, source: int): - self.openocd.write_word(DMA_CHANNEL_SOURCE(1), source) - - def set_destination(self, source: int): - self.openocd.write_word(DMA_CHANNEL_DESTINATION(1), source) - - def set_length(self, source: int): - self.openocd.write_word(DMA_CHANNEL_LEN(1), source) - - def set_config(self, source: int): - self.openocd.write_word(DMA_CHANNEL_CONFIG(1), source) - - def start( - self, - source_address: int, - destination_address: int, - length: int, - ): - self.write_buffer |= (DMA_CFG_CH_ENABLE_M - | (self.priority.value << DMA_CFG_CH_PRIOR_S) - | (self.read_mode.value << DMA_CFG_CH_READ_MODE_S) - | (self.read_increment.value << DMA_CFG_CH_READ_INCREMENT_S) - | (self.read_size.value << DMA_CFG_CH_READ_SIZE_S) - | (self.read_burst_size << DMA_CFG_CH_READ_BURST_SIZE_S) - | (self.read_request.value << DMA_CFG_CH_READ_REQ_S) - | (self.read_ack.value << DMA_CFG_CH_ACK_READ_S) - | (self.write_mode.value << DMA_CFG_CH_WRITE_MODE_S) - | (self.write_increment.value << DMA_CFG_CH_WRITE_INCREMENT_S) - | (self.write_size.value << DMA_CFG_CH_WRITE_SIZE_S) - | (self.write_burst_size << DMA_CFG_CH_WRITE_BURST_SIZE_S) - | (self.write_request.value << DMA_CFG_CH_WRITE_REQ_S) - | (self.write_ack.value << DMA_CFG_CH_ACK_WRITE_S)) - - self.openocd.write_memory(DMA_CHANNEL_DESTINATION(1), 32, [destination_address, source_address, length, self.write_buffer]) - - -class DMA: - openocd: OpenOcdTclRpc - - current_value: CurrentValue = CurrentValue.ENABLE - write_buffer: int = 0 - - channels: List[DMA_Channel] = [] - - def __init__(self, openocd: OpenOcdTclRpc): - self.openocd = openocd - self.channels.append(DMA_Channel(self.openocd)) - self.channels.append(DMA_Channel(self.openocd)) - self.channels.append(DMA_Channel(self.openocd)) - self.channels.append(DMA_Channel(self.openocd)) - - def init(self): - self.current_value = CurrentValue.ENABLE - - self.write_buffer = 0 - self.openocd.write_memory(0x40000, 32, [0] * 16) - self.clear_irq() - self.set_current_value(self.current_value) - - def set_control(self, control: int): - if (control > 2**32 or control < 0): - raise ValueError - - self.openocd.write_word(DMA_CONTROL, control) - - def get_control(self) -> int: - return self.openocd.read_word(DMA_CONTROL) - - def clear_irq(self): - self.clear_local_irq() - self.clear_global_irq() - self.clear_error_irq() - - def clear_local_irq(self): - self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M | - DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M) - self.write_buffer |= DMA_CONTROL_CLEAR_LOCAL_IRQ_M - self.set_control(self.write_buffer) - self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M | - DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M) - - def clear_global_irq(self): - self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M | - DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M) - self.write_buffer |= DMA_CONTROL_CLEAR_GLOBAL_IRQ_M - self.set_control(self.write_buffer) - self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M | - DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M) - - def clear_error_irq(self): - self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M | - DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M) - self.write_buffer |= DMA_CONTROL_CLEAR_ERROR_IRQ_M - self.set_control(self.write_buffer) - self.write_buffer &= ~(DMA_CONTROL_CLEAR_LOCAL_IRQ_M | - DMA_CONTROL_CLEAR_GLOBAL_IRQ_M | DMA_CONTROL_CLEAR_ERROR_IRQ_M) - - def set_current_value(self, current_value: CurrentValue): - self.current_value = current_value - self.write_buffer &= ~(DMA_CONTROL_CURRENT_VALUE_M) - self.write_buffer |= current_value.value << DMA_CONTROL_CURRENT_VALUE_S - self.set_control(self.write_buffer) - - def dma_wait(self, channel: DMA_Channel, timeout: float): - channel_index = channel.channel.value - mask = (1 << channel_index) << DMA_STATUS_READY_S - - begin = time.perf_counter() - - while (begin - time.perf_counter()) < timeout: - if self.get_control() & mask != 0: - return - - raise Exception - diff --git a/mik32_pm.py b/mik32_pm.py deleted file mode 100644 index 8556356..0000000 --- a/mik32_pm.py +++ /dev/null @@ -1,144 +0,0 @@ -# -------------------------- -# PM register offset -# -------------------------- -from tclrpc import OpenOcdTclRpc - - -PM_BASE_ADDRESS = 0x000050000 - -PM_Clk_AHB_Set_OFFSET = 0x0C -PM_Clk_APB_M_Set_OFFSET = 0x14 -PM_Clk_APB_P_Set_OFFSET = 0x1C - -# -------------------------- -# PM register fields -# -------------------------- - -# AHB BUS -PM_CLOCK_AHB_CPU_S = 0 -PM_CLOCK_AHB_CPU_M = (1 << PM_CLOCK_AHB_CPU_S) -PM_CLOCK_AHB_EEPROM_S = 1 -PM_CLOCK_AHB_EEPROM_M = (1 << PM_CLOCK_AHB_EEPROM_S) -PM_CLOCK_AHB_RAM_S = 2 -PM_CLOCK_AHB_RAM_M = (1 << PM_CLOCK_AHB_RAM_S) -PM_CLOCK_AHB_SPIFI_S = 3 -PM_CLOCK_AHB_SPIFI_M = (1 << PM_CLOCK_AHB_SPIFI_S) -PM_CLOCK_AHB_TCB_S = 4 -PM_CLOCK_AHB_TCB_M = (1 << PM_CLOCK_AHB_TCB_S) -PM_CLOCK_AHB_DMA_S = 5 -PM_CLOCK_AHB_DMA_M = (1 << PM_CLOCK_AHB_DMA_S) -PM_CLOCK_AHB_CRYPTO_S = 6 -PM_CLOCK_AHB_CRYPTO_M = (1 << PM_CLOCK_AHB_CRYPTO_S) -PM_CLOCK_AHB_CRC32_S = 7 -PM_CLOCK_AHB_CRC32_M = (1 << PM_CLOCK_AHB_CRC32_S) - -# APB M -PM_CLOCK_APB_M_PM_S = 0 -PM_CLOCK_APB_M_PM_M = (1 << PM_CLOCK_APB_M_PM_S) -PM_CLOCK_APB_M_EPIC_S = 1 -PM_CLOCK_APB_M_EPIC_M = (1 << PM_CLOCK_APB_M_EPIC_S) -PM_CLOCK_APB_M_TIMER32_0_S = 2 -PM_CLOCK_APB_M_TIMER32_0_M = (1 << PM_CLOCK_APB_M_TIMER32_0_S) -PM_CLOCK_APB_M_PAD_CONFIG_S = 3 -PM_CLOCK_APB_M_PAD_CONFIG_M = (1 << PM_CLOCK_APB_M_PAD_CONFIG_S) -PM_CLOCK_APB_M_WDT_BUS_S = 4 -PM_CLOCK_APB_M_WDT_BUS_M = (1 << PM_CLOCK_APB_M_WDT_BUS_S) -PM_CLOCK_APB_M_OTP_S = 5 -PM_CLOCK_APB_M_OTP_M = (1 << PM_CLOCK_APB_M_OTP_S) -PM_CLOCK_APB_M_PMON_S = 6 -PM_CLOCK_APB_M_PMON_M = (1 << PM_CLOCK_APB_M_PMON_S) -PM_CLOCK_APB_M_WU_S = 7 -PM_CLOCK_APB_M_WU_M = (1 << PM_CLOCK_APB_M_WU_S) -PM_CLOCK_APB_M_RTC_S = 8 -PM_CLOCK_APB_M_RTC_M = (1 << PM_CLOCK_APB_M_RTC_S) - -# APB_P -PM_CLOCK_APB_P_WDT_S = 0 -PM_CLOCK_APB_P_WDT_M = (1 << PM_CLOCK_APB_P_WDT_S) -PM_CLOCK_APB_P_UART_0_S = 1 -PM_CLOCK_APB_P_UART_0_M = (1 << PM_CLOCK_APB_P_UART_0_S) -PM_CLOCK_APB_P_UART_1_S = 2 -PM_CLOCK_APB_P_UART_1_M = (1 << PM_CLOCK_APB_P_UART_1_S) -PM_CLOCK_APB_P_TIMER16_0_S = 3 -PM_CLOCK_APB_P_TIMER16_0_M = (1 << PM_CLOCK_APB_P_TIMER16_0_S) -PM_CLOCK_APB_P_TIMER16_1_S = 4 -PM_CLOCK_APB_P_TIMER16_1_M = (1 << PM_CLOCK_APB_P_TIMER16_1_S) -PM_CLOCK_APB_P_TIMER16_2_S = 5 -PM_CLOCK_APB_P_TIMER16_2_M = (1 << PM_CLOCK_APB_P_TIMER16_2_S) -PM_CLOCK_APB_P_TIMER32_1_S = 6 -PM_CLOCK_APB_P_TIMER32_1_M = (1 << PM_CLOCK_APB_P_TIMER32_1_S) -PM_CLOCK_APB_P_TIMER32_2_S = 7 -PM_CLOCK_APB_P_TIMER32_2_M = (1 << PM_CLOCK_APB_P_TIMER32_2_S) -PM_CLOCK_APB_P_SPI_0_S = 8 -PM_CLOCK_APB_P_SPI_0_M = (1 << PM_CLOCK_APB_P_SPI_0_S) -PM_CLOCK_APB_P_SPI_1_S = 9 -PM_CLOCK_APB_P_SPI_1_M = (1 << PM_CLOCK_APB_P_SPI_1_S) -PM_CLOCK_APB_P_I2C_0_S = 10 -PM_CLOCK_APB_P_I2C_0_M = (1 << PM_CLOCK_APB_P_I2C_0_S) -PM_CLOCK_APB_P_I2C_1_S = 11 -PM_CLOCK_APB_P_I2C_1_M = (1 << PM_CLOCK_APB_P_I2C_1_S) -PM_CLOCK_APB_P_GPIO_0_S = 12 -PM_CLOCK_APB_P_GPIO_0_M = (1 << PM_CLOCK_APB_P_GPIO_0_S) -PM_CLOCK_APB_P_GPIO_1_S = 13 -PM_CLOCK_APB_P_GPIO_1_M = (1 << PM_CLOCK_APB_P_GPIO_1_S) -PM_CLOCK_APB_P_GPIO_2_S = 14 -PM_CLOCK_APB_P_GPIO_2_M = (1 << PM_CLOCK_APB_P_GPIO_2_S) -PM_CLOCK_APB_P_ANALOG_S = 15 -PM_CLOCK_APB_P_ANALOG_M = (1 << PM_CLOCK_APB_P_ANALOG_S) -PM_CLOCK_APB_P_GPIO_IRQ_S = 16 -PM_CLOCK_APB_P_GPIO_IRQ_M = (1 << PM_CLOCK_APB_P_GPIO_IRQ_S) - -# -------------------------- -# WU register offset -# -------------------------- -WU_BASE_ADDRESS = 0x00060000 - -WU_CLOCKS_BU_OFFSET = 0x10 - -# -------------------------- -# WU register fields -# -------------------------- - -# CLOCKS_BU -CLOCKS_BU_OCS32K_EN_S = 0 -CLOCKS_BU_OCS32K_EN_M = (1 << CLOCKS_BU_OCS32K_EN_S) -CLOCKS_BU_RC32K_EN_S = 1 -CLOCKS_BU_RC32K_EN_M = (1 << CLOCKS_BU_RC32K_EN_S) -CLOCKS_BU_ADJ_RC32K_S = 2 -CLOCKS_BU_ADJ_RC32K_M = (0b11111111 << CLOCKS_BU_ADJ_RC32K_S) -CLOCKS_BU_RTC_CLK_MUX_S = 10 -CLOCKS_BU_RTC_CLK_MUX_M = (1 << CLOCKS_BU_RTC_CLK_MUX_S) -CLOCKS_BU_OSC32K_SM_S = 14 -CLOCKS_BU_OSC32K_SM_M = (1 << CLOCKS_BU_OSC32K_SM_S) - - -def pm_init(openocd: OpenOcdTclRpc): - - WU_CLOCKS_default = 128 << CLOCKS_BU_ADJ_RC32K_S - - AHB_default = ( - PM_CLOCK_AHB_CPU_M | - PM_CLOCK_AHB_EEPROM_M | - PM_CLOCK_AHB_RAM_M | - PM_CLOCK_AHB_SPIFI_M | - PM_CLOCK_AHB_TCB_M | - PM_CLOCK_AHB_DMA_M - ) - # 0x1F - APB_M_default = ( - PM_CLOCK_APB_M_PM_M | - PM_CLOCK_APB_M_PAD_CONFIG_M | - PM_CLOCK_APB_M_WU_M - ) - # 0x89 - APB_P_default = PM_CLOCK_APB_P_GPIO_2_M - # 0x00 - - openocd.halt() - openocd.write_word(WU_BASE_ADDRESS + - WU_CLOCKS_BU_OFFSET, WU_CLOCKS_default) - openocd.write_word(PM_BASE_ADDRESS + - PM_Clk_APB_P_Set_OFFSET, APB_P_default) - openocd.write_word(PM_BASE_ADDRESS + - PM_Clk_APB_M_Set_OFFSET, APB_M_default) - openocd.write_word(PM_BASE_ADDRESS + PM_Clk_AHB_Set_OFFSET, AHB_default) diff --git a/mik32_upload.py b/mik32_upload.py index ca05bff..bde35eb 100644 --- a/mik32_upload.py +++ b/mik32_upload.py @@ -8,11 +8,11 @@ from enum import Enum from typing import List, Dict, NamedTuple, Union from hex_parser import FirmwareFile, MemorySection, MemoryType, Segment from tclrpc import OpenOcdTclRpc, TclException -from mik32_gpio import MIK32_Version, gpio_init, gpio_deinit -import mik32_eeprom -import mik32_spifi -import mik32_ram -import mik32_pm +from mik32_debug_hal.gpio import MIK32_Version, gpio_init, gpio_deinit +import mik32_debug_hal.eeprom as eeprom +import mik32_debug_hal.spifi as spifi +import mik32_debug_hal.ram as ram +import mik32_debug_hal.power_manager as power_manager from parsers import * import logging import sys @@ -242,14 +242,14 @@ def upload_file( logging.debug("OpenOCD configured!") - mik32_pm.pm_init(openocd) + power_manager.pm_init(openocd) logging.debug("PM configured!") if (pages.pages_eeprom.__len__() > 0): start_time = time.perf_counter() - result |= mik32_eeprom.write_pages( + result |= eeprom.write_pages( pages.pages_eeprom, openocd) write_time = time.perf_counter() - start_time @@ -263,7 +263,7 @@ def upload_file( gpio_init(openocd, mik_version) start_time = time.perf_counter() - result |= mik32_spifi.write_pages( + result |= spifi.write_pages( pages.pages_spifi, openocd, use_quad_spi=use_quad_spi) write_time = time.perf_counter() - start_time @@ -278,7 +278,7 @@ def upload_file( segments_ram = list(filter( lambda segment: (segment.memory is not None) and (segment.memory.type == MemoryType.RAM), segments)) if (segments_ram.__len__() > 0): - mik32_ram.write_segments(segments_ram, openocd) + ram.write_segments(segments_ram, openocd) result |= 0 openocd.run(post_action)