mirror of
https://github.com/MikronMIK32/mik32-uploader.git
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Merge pull request #1 from MikronMIK32/improve-pm-control
Improve pm control and fix whitespaces problem
This commit is contained in:
sh-sergey
GitHub
commit
8c84f3a68c
@ -4,46 +4,6 @@ import time
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from tclrpc import OpenOcdTclRpc
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from utils import bytes2words
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# --------------------------
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# PM register offset
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# --------------------------
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PM_BASE_ADDRESS = 0x000050000
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PM_Clk_AHB_Set_OFFSET = 0x0C
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PM_Clk_APB_M_Set_OFFSET = 0x14
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PM_Clk_APB_P_Set_OFFSET = 0x1C
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# --------------------------
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# PM register fields
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# --------------------------
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# AHB BUS
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PM_CLOCK_CPU_S = 0
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PM_CLOCK_CPU_M = (1 << PM_CLOCK_CPU_S)
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PM_CLOCK_EEPROM_S = 1
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PM_CLOCK_EEPROM_M = (1 << PM_CLOCK_EEPROM_S)
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PM_CLOCK_RAM_S = 2
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PM_CLOCK_RAM_M = (1 << PM_CLOCK_RAM_S)
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PM_CLOCK_SPIFI_S = 3
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PM_CLOCK_SPIFI_M = (1 << PM_CLOCK_SPIFI_S)
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PM_CLOCK_TCB_S = 4
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PM_CLOCK_TCB_M = (1 << PM_CLOCK_TCB_S)
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PM_CLOCK_DMA_S = 5
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PM_CLOCK_DMA_M = (1 << PM_CLOCK_DMA_S)
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PM_CLOCK_CRYPTO_S = 6
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PM_CLOCK_CRYPTO_M = (1 << PM_CLOCK_CRYPTO_S)
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PM_CLOCK_CRC32_S = 7
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PM_CLOCK_CRC32_M = (1 << PM_CLOCK_CRC32_S)
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# APB M
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PM_CLOCK_PM_S = 0
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PM_CLOCK_PM_M = (1 << PM_CLOCK_PM_S)
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# --------------------------
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# WU register offset
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# --------------------------
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WU_BASE_ADDRESS = 0x00060000
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WU_Clocks_OFFSET = 0x10
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# --------------------------
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# EEPROM register offset
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@ -94,11 +54,6 @@ EEPROM_PAGE_MASK = 0x1F80
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def eeprom_sysinit(openocd: OpenOcdTclRpc):
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print("MCU clock init...", flush=True)
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openocd.write_word(WU_BASE_ADDRESS + WU_Clocks_OFFSET, 0x202)
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openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_P_Set_OFFSET, 0xffffffff)
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openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_M_Set_OFFSET, 0xffffffff)
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openocd.write_word(PM_BASE_ADDRESS + PM_Clk_AHB_Set_OFFSET, 0xffffffff)
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class EEPROM_Operation(Enum):
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READ = EEPROM_OP_RD
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144
mik32_pm.py
Normal file
144
mik32_pm.py
Normal file
@ -0,0 +1,144 @@
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# --------------------------
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# PM register offset
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# --------------------------
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from tclrpc import OpenOcdTclRpc
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PM_BASE_ADDRESS = 0x000050000
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PM_Clk_AHB_Set_OFFSET = 0x0C
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PM_Clk_APB_M_Set_OFFSET = 0x14
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PM_Clk_APB_P_Set_OFFSET = 0x1C
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# --------------------------
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# PM register fields
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# --------------------------
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# AHB BUS
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PM_CLOCK_AHB_CPU_S = 0
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PM_CLOCK_AHB_CPU_M = (1 << PM_CLOCK_AHB_CPU_S)
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PM_CLOCK_AHB_EEPROM_S = 1
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PM_CLOCK_AHB_EEPROM_M = (1 << PM_CLOCK_AHB_EEPROM_S)
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PM_CLOCK_AHB_RAM_S = 2
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PM_CLOCK_AHB_RAM_M = (1 << PM_CLOCK_AHB_RAM_S)
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PM_CLOCK_AHB_SPIFI_S = 3
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PM_CLOCK_AHB_SPIFI_M = (1 << PM_CLOCK_AHB_SPIFI_S)
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PM_CLOCK_AHB_TCB_S = 4
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PM_CLOCK_AHB_TCB_M = (1 << PM_CLOCK_AHB_TCB_S)
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PM_CLOCK_AHB_DMA_S = 5
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PM_CLOCK_AHB_DMA_M = (1 << PM_CLOCK_AHB_DMA_S)
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PM_CLOCK_AHB_CRYPTO_S = 6
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PM_CLOCK_AHB_CRYPTO_M = (1 << PM_CLOCK_AHB_CRYPTO_S)
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PM_CLOCK_AHB_CRC32_S = 7
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PM_CLOCK_AHB_CRC32_M = (1 << PM_CLOCK_AHB_CRC32_S)
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# APB M
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PM_CLOCK_APB_M_PM_S = 0
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PM_CLOCK_APB_M_PM_M = (1 << PM_CLOCK_APB_M_PM_S)
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PM_CLOCK_APB_M_EPIC_S = 1
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PM_CLOCK_APB_M_EPIC_M = (1 << PM_CLOCK_APB_M_EPIC_S)
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PM_CLOCK_APB_M_TIMER32_0_S = 2
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PM_CLOCK_APB_M_TIMER32_0_M = (1 << PM_CLOCK_APB_M_TIMER32_0_S)
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PM_CLOCK_APB_M_PAD_CONFIG_S = 3
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PM_CLOCK_APB_M_PAD_CONFIG_M = (1 << PM_CLOCK_APB_M_PAD_CONFIG_S)
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PM_CLOCK_APB_M_WDT_BUS_S = 4
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PM_CLOCK_APB_M_WDT_BUS_M = (1 << PM_CLOCK_APB_M_WDT_BUS_S)
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PM_CLOCK_APB_M_OTP_S = 5
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PM_CLOCK_APB_M_OTP_M = (1 << PM_CLOCK_APB_M_OTP_S)
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PM_CLOCK_APB_M_PMON_S = 6
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PM_CLOCK_APB_M_PMON_M = (1 << PM_CLOCK_APB_M_PMON_S)
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PM_CLOCK_APB_M_WU_S = 7
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PM_CLOCK_APB_M_WU_M = (1 << PM_CLOCK_APB_M_WU_S)
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PM_CLOCK_APB_M_RTC_S = 8
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PM_CLOCK_APB_M_RTC_M = (1 << PM_CLOCK_APB_M_RTC_S)
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# APB_P
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PM_CLOCK_APB_P_WDT_S = 0
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PM_CLOCK_APB_P_WDT_M = (1 << PM_CLOCK_APB_P_WDT_S)
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PM_CLOCK_APB_P_UART_0_S = 1
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PM_CLOCK_APB_P_UART_0_M = (1 << PM_CLOCK_APB_P_UART_0_S)
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PM_CLOCK_APB_P_UART_1_S = 2
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PM_CLOCK_APB_P_UART_1_M = (1 << PM_CLOCK_APB_P_UART_1_S)
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PM_CLOCK_APB_P_TIMER16_0_S = 3
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PM_CLOCK_APB_P_TIMER16_0_M = (1 << PM_CLOCK_APB_P_TIMER16_0_S)
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PM_CLOCK_APB_P_TIMER16_1_S = 4
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PM_CLOCK_APB_P_TIMER16_1_M = (1 << PM_CLOCK_APB_P_TIMER16_1_S)
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PM_CLOCK_APB_P_TIMER16_2_S = 5
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PM_CLOCK_APB_P_TIMER16_2_M = (1 << PM_CLOCK_APB_P_TIMER16_2_S)
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PM_CLOCK_APB_P_TIMER32_1_S = 6
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PM_CLOCK_APB_P_TIMER32_1_M = (1 << PM_CLOCK_APB_P_TIMER32_1_S)
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PM_CLOCK_APB_P_TIMER32_2_S = 7
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PM_CLOCK_APB_P_TIMER32_2_M = (1 << PM_CLOCK_APB_P_TIMER32_2_S)
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PM_CLOCK_APB_P_SPI_0_S = 8
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PM_CLOCK_APB_P_SPI_0_M = (1 << PM_CLOCK_APB_P_SPI_0_S)
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PM_CLOCK_APB_P_SPI_1_S = 9
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PM_CLOCK_APB_P_SPI_1_M = (1 << PM_CLOCK_APB_P_SPI_1_S)
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PM_CLOCK_APB_P_I2C_0_S = 10
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PM_CLOCK_APB_P_I2C_0_M = (1 << PM_CLOCK_APB_P_I2C_0_S)
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PM_CLOCK_APB_P_I2C_1_S = 11
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PM_CLOCK_APB_P_I2C_1_M = (1 << PM_CLOCK_APB_P_I2C_1_S)
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PM_CLOCK_APB_P_GPIO_0_S = 12
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PM_CLOCK_APB_P_GPIO_0_M = (1 << PM_CLOCK_APB_P_GPIO_0_S)
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PM_CLOCK_APB_P_GPIO_1_S = 13
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PM_CLOCK_APB_P_GPIO_1_M = (1 << PM_CLOCK_APB_P_GPIO_1_S)
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PM_CLOCK_APB_P_GPIO_2_S = 14
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PM_CLOCK_APB_P_GPIO_2_M = (1 << PM_CLOCK_APB_P_GPIO_2_S)
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PM_CLOCK_APB_P_ANALOG_S = 15
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PM_CLOCK_APB_P_ANALOG_M = (1 << PM_CLOCK_APB_P_ANALOG_S)
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PM_CLOCK_APB_P_GPIO_IRQ_S = 16
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PM_CLOCK_APB_P_GPIO_IRQ_M = (1 << PM_CLOCK_APB_P_GPIO_IRQ_S)
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# --------------------------
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# WU register offset
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# --------------------------
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WU_BASE_ADDRESS = 0x00060000
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WU_CLOCKS_BU_OFFSET = 0x10
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# --------------------------
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# WU register fields
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# --------------------------
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# CLOCKS_BU
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CLOCKS_BU_OCS32K_EN_S = 0
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CLOCKS_BU_OCS32K_EN_M = (1 << CLOCKS_BU_OCS32K_EN_S)
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CLOCKS_BU_RC32K_EN_S = 1
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CLOCKS_BU_RC32K_EN_M = (1 << CLOCKS_BU_RC32K_EN_S)
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CLOCKS_BU_ADJ_RC32K_S = 2
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CLOCKS_BU_ADJ_RC32K_M = (0b11111111 << CLOCKS_BU_ADJ_RC32K_S)
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CLOCKS_BU_RTC_CLK_MUX_S = 10
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CLOCKS_BU_RTC_CLK_MUX_M = (1 << CLOCKS_BU_RTC_CLK_MUX_S)
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CLOCKS_BU_OSC32K_SM_S = 14
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CLOCKS_BU_OSC32K_SM_M = (1 << CLOCKS_BU_OSC32K_SM_S)
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def pm_init(openocd: OpenOcdTclRpc):
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WU_CLOCKS_default = 128 << CLOCKS_BU_ADJ_RC32K_S
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AHB_default = (
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PM_CLOCK_AHB_CPU_M |
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PM_CLOCK_AHB_EEPROM_M |
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PM_CLOCK_AHB_RAM_M |
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PM_CLOCK_AHB_SPIFI_M |
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PM_CLOCK_AHB_TCB_M |
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PM_CLOCK_AHB_DMA_M
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)
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# 0x1F
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APB_M_default = (
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PM_CLOCK_APB_M_PM_M |
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PM_CLOCK_APB_M_PAD_CONFIG_M |
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PM_CLOCK_APB_M_WU_M
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)
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# 0x89
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APB_P_default = 0
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# 0x00
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openocd.halt()
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openocd.write_word(WU_BASE_ADDRESS +
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WU_CLOCKS_BU_OFFSET, WU_CLOCKS_default)
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openocd.write_word(PM_BASE_ADDRESS +
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PM_Clk_APB_P_Set_OFFSET, APB_P_default)
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openocd.write_word(PM_BASE_ADDRESS +
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PM_Clk_APB_M_Set_OFFSET, APB_M_default)
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openocd.write_word(PM_BASE_ADDRESS + PM_Clk_AHB_Set_OFFSET, AHB_default)
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@ -5,46 +5,6 @@ from tclrpc import TclException
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from tclrpc import OpenOcdTclRpc
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from mik32_dma import DMA, ChannelMode, ChannelIndex, ChannelAck, ChannelIncrement, ChannelPriority, ChannelRequest, ChannelSize
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# --------------------------
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# PM register offset
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# --------------------------
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PM_BASE_ADDRESS = 0x000050000
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PM_Clk_AHB_Set_OFFSET = 0x0C
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PM_Clk_APB_M_Set_OFFSET = 0x14
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PM_Clk_APB_P_Set_OFFSET = 0x1C
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# --------------------------
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# PM register fields
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# --------------------------
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# AHB BUS
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PM_CLOCK_CPU_S = 0
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PM_CLOCK_CPU_M = (1 << PM_CLOCK_CPU_S)
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PM_CLOCK_EEPROM_S = 1
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PM_CLOCK_EEPROM_M = (1 << PM_CLOCK_EEPROM_S)
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PM_CLOCK_RAM_S = 2
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PM_CLOCK_RAM_M = (1 << PM_CLOCK_RAM_S)
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PM_CLOCK_SPIFI_S = 3
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PM_CLOCK_SPIFI_M = (1 << PM_CLOCK_SPIFI_S)
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PM_CLOCK_TCB_S = 4
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PM_CLOCK_TCB_M = (1 << PM_CLOCK_TCB_S)
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PM_CLOCK_DMA_S = 5
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PM_CLOCK_DMA_M = (1 << PM_CLOCK_DMA_S)
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PM_CLOCK_CRYPTO_S = 6
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PM_CLOCK_CRYPTO_M = (1 << PM_CLOCK_CRYPTO_S)
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PM_CLOCK_CRC32_S = 7
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PM_CLOCK_CRC32_M = (1 << PM_CLOCK_CRC32_S)
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# APB M
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PM_CLOCK_PM_S = 0
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PM_CLOCK_PM_M = (1 << PM_CLOCK_PM_S)
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# --------------------------
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# WU register offset
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# --------------------------
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WU_BASE_ADDRESS = 0x00060000
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WU_Clocks_OFFSET = 0x10
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# --------------------------
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# SPIFI register offset
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@ -240,11 +200,6 @@ def spifi_init_periphery(openocd: OpenOcdTclRpc):
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def spifi_init(openocd: OpenOcdTclRpc):
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print("MCU clock init", flush=True)
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openocd.write_word(WU_BASE_ADDRESS + WU_Clocks_OFFSET, 0x202)
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openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_P_Set_OFFSET, 0xffffffff)
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openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_M_Set_OFFSET, 0xffffffff)
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openocd.write_word(PM_BASE_ADDRESS + PM_Clk_AHB_Set_OFFSET, 0xffffffff)
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spifi_init_periphery(openocd)
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control = openocd.read_word(SPIFI_CONFIG_CTRL)
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@ -1,5 +1,6 @@
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import shlex
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import argparse
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import socket
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import subprocess
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import os
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import time
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@ -9,7 +10,9 @@ from tclrpc import OpenOcdTclRpc, TclException
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import mik32_eeprom
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import mik32_spifi
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import mik32_ram
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import mik32_pm
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from mik32_parsers import *
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import logging, sys
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# class bcolors(Enum):
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@ -37,7 +40,12 @@ supported_text_formats = [".hex"]
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def test_connection():
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output = ""
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with OpenOcdTclRpc() as openocd:
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try:
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output = openocd.run("capture \"reg\"")
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except OSError:
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logging.debug("Test connection timed out, try again")
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output = openocd.run("capture \"reg\"")
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if output == "":
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raise Exception("ERROR: no regs found, check MCU connection")
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@ -218,11 +226,8 @@ def run_openocd(
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openocd_target=openocd_target_path,
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is_open_console=False
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) -> subprocess.Popen:
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print(openocd_scripts)
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cmd = shlex.split(
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f"{openocd_exec} -s {openocd_scripts} "
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f"-f {openocd_interface} -f {openocd_target}", posix=False
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)
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cmd = [openocd_exec, "-s", openocd_scripts,
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"-f", openocd_interface, "-f", openocd_target]
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creation_flags = subprocess.SW_HIDE
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if is_open_console:
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@ -308,9 +313,13 @@ def upload_file(
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proc: Union[subprocess.Popen, None] = None
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if is_run_openocd:
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try:
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logging.debug("OpenOCD try start!")
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proc = run_openocd(openocd_exec, openocd_scripts,
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openocd_interface, openocd_target, is_open_console)
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print("OpenOCD successfully started!", flush=True)
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logging.debug("OpenOCD started!")
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except OSError as e:
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raise OpenOCDStartupException(e)
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try:
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@ -320,6 +329,12 @@ def upload_file(
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openocd.run(f"log_output \"{log_path}\"")
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openocd.run(f"debug_level 1")
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logging.debug("OpenOCD configured!")
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mik32_pm.pm_init(openocd)
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logging.debug("PM configured!")
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if (pages.pages_eeprom.__len__() > 0):
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start_time = time.perf_counter()
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@ -475,6 +490,8 @@ def createParser():
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if __name__ == '__main__':
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logging.basicConfig(stream=sys.stderr, level=logging.INFO)
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parser = createParser()
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namespace = parser.parse_args()
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@ -51,6 +51,14 @@ class OpenOcdTclRpc:
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def __enter__(self):
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self.sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
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self.sock.settimeout(5.0)
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try:
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self.sock.connect((self.host, self.port))
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except socket.timeout:
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logger.debug("Test connection timed out, try again")
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self.sock.close()
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self.sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
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self.sock.settimeout(5.0)
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self.sock.connect((self.host, self.port))
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return self
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