Merge pull request #1 from MikronMIK32/improve-pm-control

Improve pm control and fix whitespaces problem

mik32_eeprom.py

@@ -4,46 +4,6 @@ import time
 from tclrpc import OpenOcdTclRpc
 from utils import bytes2words
 
-# --------------------------
-# PM register offset
-# --------------------------
-PM_BASE_ADDRESS = 0x000050000
-
-PM_Clk_AHB_Set_OFFSET = 0x0C
-PM_Clk_APB_M_Set_OFFSET = 0x14
-PM_Clk_APB_P_Set_OFFSET = 0x1C
-
-# --------------------------
-# PM register fields
-# --------------------------
-# AHB BUS
-PM_CLOCK_CPU_S = 0
-PM_CLOCK_CPU_M = (1 << PM_CLOCK_CPU_S)
-PM_CLOCK_EEPROM_S = 1
-PM_CLOCK_EEPROM_M = (1 << PM_CLOCK_EEPROM_S)
-PM_CLOCK_RAM_S = 2
-PM_CLOCK_RAM_M = (1 << PM_CLOCK_RAM_S)
-PM_CLOCK_SPIFI_S = 3
-PM_CLOCK_SPIFI_M = (1 << PM_CLOCK_SPIFI_S)
-PM_CLOCK_TCB_S = 4
-PM_CLOCK_TCB_M = (1 << PM_CLOCK_TCB_S)
-PM_CLOCK_DMA_S = 5
-PM_CLOCK_DMA_M = (1 << PM_CLOCK_DMA_S)
-PM_CLOCK_CRYPTO_S = 6
-PM_CLOCK_CRYPTO_M = (1 << PM_CLOCK_CRYPTO_S)
-PM_CLOCK_CRC32_S = 7
-PM_CLOCK_CRC32_M = (1 << PM_CLOCK_CRC32_S)
-
-# APB M
-PM_CLOCK_PM_S = 0
-PM_CLOCK_PM_M = (1 << PM_CLOCK_PM_S)
-
-# --------------------------
-# WU register offset
-# --------------------------
-WU_BASE_ADDRESS = 0x00060000
-
-WU_Clocks_OFFSET = 0x10
 
 # --------------------------
 # EEPROM register offset
@@ -94,11 +54,6 @@ EEPROM_PAGE_MASK = 0x1F80
 def eeprom_sysinit(openocd: OpenOcdTclRpc):
     print("MCU clock init...", flush=True)
 
-    openocd.write_word(WU_BASE_ADDRESS + WU_Clocks_OFFSET, 0x202)
-    openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_P_Set_OFFSET, 0xffffffff)
-    openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_M_Set_OFFSET, 0xffffffff)
-    openocd.write_word(PM_BASE_ADDRESS + PM_Clk_AHB_Set_OFFSET, 0xffffffff)
-
 
 class EEPROM_Operation(Enum):
     READ = EEPROM_OP_RD

mik32_pm.py

@@ -0,0 +1,144 @@
+# --------------------------
+# PM register offset
+# --------------------------
+from tclrpc import OpenOcdTclRpc
+
+
+PM_BASE_ADDRESS = 0x000050000
+
+PM_Clk_AHB_Set_OFFSET = 0x0C
+PM_Clk_APB_M_Set_OFFSET = 0x14
+PM_Clk_APB_P_Set_OFFSET = 0x1C
+
+# --------------------------
+# PM register fields
+# --------------------------
+
+# AHB BUS
+PM_CLOCK_AHB_CPU_S = 0
+PM_CLOCK_AHB_CPU_M = (1 << PM_CLOCK_AHB_CPU_S)
+PM_CLOCK_AHB_EEPROM_S = 1
+PM_CLOCK_AHB_EEPROM_M = (1 << PM_CLOCK_AHB_EEPROM_S)
+PM_CLOCK_AHB_RAM_S = 2
+PM_CLOCK_AHB_RAM_M = (1 << PM_CLOCK_AHB_RAM_S)
+PM_CLOCK_AHB_SPIFI_S = 3
+PM_CLOCK_AHB_SPIFI_M = (1 << PM_CLOCK_AHB_SPIFI_S)
+PM_CLOCK_AHB_TCB_S = 4
+PM_CLOCK_AHB_TCB_M = (1 << PM_CLOCK_AHB_TCB_S)
+PM_CLOCK_AHB_DMA_S = 5
+PM_CLOCK_AHB_DMA_M = (1 << PM_CLOCK_AHB_DMA_S)
+PM_CLOCK_AHB_CRYPTO_S = 6
+PM_CLOCK_AHB_CRYPTO_M = (1 << PM_CLOCK_AHB_CRYPTO_S)
+PM_CLOCK_AHB_CRC32_S = 7
+PM_CLOCK_AHB_CRC32_M = (1 << PM_CLOCK_AHB_CRC32_S)
+
+# APB M
+PM_CLOCK_APB_M_PM_S = 0
+PM_CLOCK_APB_M_PM_M = (1 << PM_CLOCK_APB_M_PM_S)
+PM_CLOCK_APB_M_EPIC_S = 1
+PM_CLOCK_APB_M_EPIC_M = (1 << PM_CLOCK_APB_M_EPIC_S)
+PM_CLOCK_APB_M_TIMER32_0_S = 2
+PM_CLOCK_APB_M_TIMER32_0_M = (1 << PM_CLOCK_APB_M_TIMER32_0_S)
+PM_CLOCK_APB_M_PAD_CONFIG_S = 3
+PM_CLOCK_APB_M_PAD_CONFIG_M = (1 << PM_CLOCK_APB_M_PAD_CONFIG_S)
+PM_CLOCK_APB_M_WDT_BUS_S = 4
+PM_CLOCK_APB_M_WDT_BUS_M = (1 << PM_CLOCK_APB_M_WDT_BUS_S)
+PM_CLOCK_APB_M_OTP_S = 5
+PM_CLOCK_APB_M_OTP_M = (1 << PM_CLOCK_APB_M_OTP_S)
+PM_CLOCK_APB_M_PMON_S = 6
+PM_CLOCK_APB_M_PMON_M = (1 << PM_CLOCK_APB_M_PMON_S)
+PM_CLOCK_APB_M_WU_S = 7
+PM_CLOCK_APB_M_WU_M = (1 << PM_CLOCK_APB_M_WU_S)
+PM_CLOCK_APB_M_RTC_S = 8
+PM_CLOCK_APB_M_RTC_M = (1 << PM_CLOCK_APB_M_RTC_S)
+
+# APB_P
+PM_CLOCK_APB_P_WDT_S = 0
+PM_CLOCK_APB_P_WDT_M = (1 << PM_CLOCK_APB_P_WDT_S)
+PM_CLOCK_APB_P_UART_0_S = 1
+PM_CLOCK_APB_P_UART_0_M = (1 << PM_CLOCK_APB_P_UART_0_S)
+PM_CLOCK_APB_P_UART_1_S = 2
+PM_CLOCK_APB_P_UART_1_M = (1 << PM_CLOCK_APB_P_UART_1_S)
+PM_CLOCK_APB_P_TIMER16_0_S = 3
+PM_CLOCK_APB_P_TIMER16_0_M = (1 << PM_CLOCK_APB_P_TIMER16_0_S)
+PM_CLOCK_APB_P_TIMER16_1_S = 4
+PM_CLOCK_APB_P_TIMER16_1_M = (1 << PM_CLOCK_APB_P_TIMER16_1_S)
+PM_CLOCK_APB_P_TIMER16_2_S = 5
+PM_CLOCK_APB_P_TIMER16_2_M = (1 << PM_CLOCK_APB_P_TIMER16_2_S)
+PM_CLOCK_APB_P_TIMER32_1_S = 6
+PM_CLOCK_APB_P_TIMER32_1_M = (1 << PM_CLOCK_APB_P_TIMER32_1_S)
+PM_CLOCK_APB_P_TIMER32_2_S = 7
+PM_CLOCK_APB_P_TIMER32_2_M = (1 << PM_CLOCK_APB_P_TIMER32_2_S)
+PM_CLOCK_APB_P_SPI_0_S = 8
+PM_CLOCK_APB_P_SPI_0_M = (1 << PM_CLOCK_APB_P_SPI_0_S)
+PM_CLOCK_APB_P_SPI_1_S = 9
+PM_CLOCK_APB_P_SPI_1_M = (1 << PM_CLOCK_APB_P_SPI_1_S)
+PM_CLOCK_APB_P_I2C_0_S = 10
+PM_CLOCK_APB_P_I2C_0_M = (1 << PM_CLOCK_APB_P_I2C_0_S)
+PM_CLOCK_APB_P_I2C_1_S = 11
+PM_CLOCK_APB_P_I2C_1_M = (1 << PM_CLOCK_APB_P_I2C_1_S)
+PM_CLOCK_APB_P_GPIO_0_S = 12
+PM_CLOCK_APB_P_GPIO_0_M = (1 << PM_CLOCK_APB_P_GPIO_0_S)
+PM_CLOCK_APB_P_GPIO_1_S = 13
+PM_CLOCK_APB_P_GPIO_1_M = (1 << PM_CLOCK_APB_P_GPIO_1_S)
+PM_CLOCK_APB_P_GPIO_2_S = 14
+PM_CLOCK_APB_P_GPIO_2_M = (1 << PM_CLOCK_APB_P_GPIO_2_S)
+PM_CLOCK_APB_P_ANALOG_S = 15
+PM_CLOCK_APB_P_ANALOG_M = (1 << PM_CLOCK_APB_P_ANALOG_S)
+PM_CLOCK_APB_P_GPIO_IRQ_S = 16
+PM_CLOCK_APB_P_GPIO_IRQ_M = (1 << PM_CLOCK_APB_P_GPIO_IRQ_S)
+
+# --------------------------
+# WU register offset
+# --------------------------
+WU_BASE_ADDRESS = 0x00060000
+
+WU_CLOCKS_BU_OFFSET = 0x10
+
+# --------------------------
+# WU register fields
+# --------------------------
+
+# CLOCKS_BU
+CLOCKS_BU_OCS32K_EN_S = 0
+CLOCKS_BU_OCS32K_EN_M = (1 << CLOCKS_BU_OCS32K_EN_S)
+CLOCKS_BU_RC32K_EN_S = 1
+CLOCKS_BU_RC32K_EN_M = (1 << CLOCKS_BU_RC32K_EN_S)
+CLOCKS_BU_ADJ_RC32K_S = 2
+CLOCKS_BU_ADJ_RC32K_M = (0b11111111 << CLOCKS_BU_ADJ_RC32K_S)
+CLOCKS_BU_RTC_CLK_MUX_S = 10
+CLOCKS_BU_RTC_CLK_MUX_M = (1 << CLOCKS_BU_RTC_CLK_MUX_S)
+CLOCKS_BU_OSC32K_SM_S = 14
+CLOCKS_BU_OSC32K_SM_M = (1 << CLOCKS_BU_OSC32K_SM_S)
+
+
+def pm_init(openocd: OpenOcdTclRpc):
+
+    WU_CLOCKS_default = 128 << CLOCKS_BU_ADJ_RC32K_S
+
+    AHB_default = (
+        PM_CLOCK_AHB_CPU_M |
+        PM_CLOCK_AHB_EEPROM_M |
+        PM_CLOCK_AHB_RAM_M |
+        PM_CLOCK_AHB_SPIFI_M |
+        PM_CLOCK_AHB_TCB_M |
+        PM_CLOCK_AHB_DMA_M
+    )
+    # 0x1F
+    APB_M_default = (
+        PM_CLOCK_APB_M_PM_M |
+        PM_CLOCK_APB_M_PAD_CONFIG_M |
+        PM_CLOCK_APB_M_WU_M
+    )
+    # 0x89
+    APB_P_default = 0
+    # 0x00
+
+    openocd.halt()
+    openocd.write_word(WU_BASE_ADDRESS +
+                       WU_CLOCKS_BU_OFFSET, WU_CLOCKS_default)
+    openocd.write_word(PM_BASE_ADDRESS +
+                       PM_Clk_APB_P_Set_OFFSET, APB_P_default)
+    openocd.write_word(PM_BASE_ADDRESS +
+                       PM_Clk_APB_M_Set_OFFSET, APB_M_default)
+    openocd.write_word(PM_BASE_ADDRESS + PM_Clk_AHB_Set_OFFSET, AHB_default)

mik32_spifi.py

@@ -5,46 +5,6 @@ from tclrpc import TclException
 from tclrpc import OpenOcdTclRpc
 from mik32_dma import DMA, ChannelMode, ChannelIndex, ChannelAck, ChannelIncrement, ChannelPriority, ChannelRequest, ChannelSize
 
-# --------------------------
-# PM register offset
-# --------------------------
-PM_BASE_ADDRESS = 0x000050000
-
-PM_Clk_AHB_Set_OFFSET = 0x0C
-PM_Clk_APB_M_Set_OFFSET = 0x14
-PM_Clk_APB_P_Set_OFFSET = 0x1C
-
-# --------------------------
-# PM register fields
-# --------------------------
-# AHB BUS
-PM_CLOCK_CPU_S = 0
-PM_CLOCK_CPU_M = (1 << PM_CLOCK_CPU_S)
-PM_CLOCK_EEPROM_S = 1
-PM_CLOCK_EEPROM_M = (1 << PM_CLOCK_EEPROM_S)
-PM_CLOCK_RAM_S = 2
-PM_CLOCK_RAM_M = (1 << PM_CLOCK_RAM_S)
-PM_CLOCK_SPIFI_S = 3
-PM_CLOCK_SPIFI_M = (1 << PM_CLOCK_SPIFI_S)
-PM_CLOCK_TCB_S = 4
-PM_CLOCK_TCB_M = (1 << PM_CLOCK_TCB_S)
-PM_CLOCK_DMA_S = 5
-PM_CLOCK_DMA_M = (1 << PM_CLOCK_DMA_S)
-PM_CLOCK_CRYPTO_S = 6
-PM_CLOCK_CRYPTO_M = (1 << PM_CLOCK_CRYPTO_S)
-PM_CLOCK_CRC32_S = 7
-PM_CLOCK_CRC32_M = (1 << PM_CLOCK_CRC32_S)
-
-# APB M
-PM_CLOCK_PM_S = 0
-PM_CLOCK_PM_M = (1 << PM_CLOCK_PM_S)
-
-# --------------------------
-# WU register offset
-# --------------------------
-WU_BASE_ADDRESS = 0x00060000
-
-WU_Clocks_OFFSET = 0x10
 
 # --------------------------
 # SPIFI register offset
@@ -240,11 +200,6 @@ def spifi_init_periphery(openocd: OpenOcdTclRpc):
 def spifi_init(openocd: OpenOcdTclRpc):
     print("MCU clock init", flush=True)
 
-    openocd.write_word(WU_BASE_ADDRESS + WU_Clocks_OFFSET, 0x202)
-    openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_P_Set_OFFSET, 0xffffffff)
-    openocd.write_word(PM_BASE_ADDRESS + PM_Clk_APB_M_Set_OFFSET, 0xffffffff)
-    openocd.write_word(PM_BASE_ADDRESS + PM_Clk_AHB_Set_OFFSET, 0xffffffff)
-
     spifi_init_periphery(openocd)
 
     control = openocd.read_word(SPIFI_CONFIG_CTRL)

mik32_upload.py

@@ -1,5 +1,6 @@
 import shlex
 import argparse
+import socket
 import subprocess
 import os
 import time
@@ -9,7 +10,9 @@ from tclrpc import OpenOcdTclRpc, TclException
 import mik32_eeprom
 import mik32_spifi
 import mik32_ram
+import mik32_pm
 from mik32_parsers import *
+import logging, sys
 
 
 # class bcolors(Enum):
@@ -37,7 +40,12 @@ supported_text_formats = [".hex"]
 def test_connection():
     output = ""
     with OpenOcdTclRpc() as openocd:
+        try:
             output = openocd.run("capture \"reg\"")
+        except OSError:
+            logging.debug("Test connection timed out, try again")
+            output = openocd.run("capture \"reg\"")
+            
 
     if output == "":
         raise Exception("ERROR: no regs found, check MCU connection")
@@ -218,11 +226,8 @@ def run_openocd(
     openocd_target=openocd_target_path,
     is_open_console=False
 ) -> subprocess.Popen:
-    print(openocd_scripts)
+    cmd = [openocd_exec, "-s", openocd_scripts,
-    cmd = shlex.split(
+        "-f", openocd_interface, "-f", openocd_target]
-        f"{openocd_exec} -s {openocd_scripts} "
-        f"-f {openocd_interface} -f {openocd_target}", posix=False
-    )
 
     creation_flags = subprocess.SW_HIDE
     if is_open_console:
@@ -308,9 +313,13 @@ def upload_file(
     proc: Union[subprocess.Popen, None] = None
     if is_run_openocd:
         try:
+            logging.debug("OpenOCD try start!")
+
             proc = run_openocd(openocd_exec, openocd_scripts,
                                openocd_interface, openocd_target, is_open_console)
-            print("OpenOCD successfully started!", flush=True)
+
+            logging.debug("OpenOCD started!")
+            
         except OSError as e:
             raise OpenOCDStartupException(e)
     try:
@@ -320,6 +329,12 @@ def upload_file(
             openocd.run(f"log_output \"{log_path}\"")
             openocd.run(f"debug_level 1")
 
+            logging.debug("OpenOCD configured!")
+
+            mik32_pm.pm_init(openocd)
+
+            logging.debug("PM configured!")
+
             if (pages.pages_eeprom.__len__() > 0):
                 start_time = time.perf_counter()
 
@@ -475,6 +490,8 @@ def createParser():
 
 
 if __name__ == '__main__':
+    logging.basicConfig(stream=sys.stderr, level=logging.INFO)
+
     parser = createParser()
     namespace = parser.parse_args()
 

tclrpc.py

@@ -51,6 +51,14 @@ class OpenOcdTclRpc:
 
     def __enter__(self):
         self.sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+        self.sock.settimeout(5.0)
+        try:
+            self.sock.connect((self.host, self.port))
+        except socket.timeout:
+            logger.debug("Test connection timed out, try again")
+            self.sock.close()
+            self.sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+            self.sock.settimeout(5.0)
             self.sock.connect((self.host, self.port))
         return self