diff --git a/mik32_parsing.py b/mik32_parsing.py
index 44aa0b3..fd3b1d7 100644
--- a/mik32_parsing.py
+++ b/mik32_parsing.py
@@ -73,7 +73,7 @@ def parse_hex(file: str) -> dict:
         elif rectype == 4:  # Extended Linear Address Record
             print("Extended Linear Address Record")
             print("ERROR: unimplemented record type 4 on line %i" % (i+1))
-            is_error = True
+            # is_error = True
         elif rectype == 5:  # Start Linear Address Record
             print("Start Linear Address is 0x%s (line %i)" %
                     (data_bytes_line, (i+1)))
diff --git a/mik32_ram.py b/mik32_ram.py
index bc758fe..de888bc 100644
--- a/mik32_ram.py
+++ b/mik32_ram.py
@@ -5,7 +5,7 @@ from pathlib import Path
 def write_file(filename):
 
     with OpenOcdTclRpc() as openocd:
-        openocd.halt()
+        openocd.reset_halt()
         print(openocd.run("load_image {%s} 0x0" % Path(filename)))
         openocd.resume(0)
     print("RAM write file maybe done")
diff --git a/tclrpc.py b/tclrpc.py
index 99437b4..6b58d82 100644
--- a/tclrpc.py
+++ b/tclrpc.py
@@ -90,6 +90,10 @@ class OpenOcdTclRpc:
             raise TclException(code, msg)
         else:
             return msg
+        
+    def reset_halt(self):
+        """Halt MCU and raise an error if it returns an error"""
+        return self.run("capture \"reset halt\"")
     
     def halt(self):
         """Halt MCU and raise an error if it returns an error"""